Duplicate wires and assign-to-self in Verilog output

[JulianKemmerer]

Description
synth --out=verilog produces duplicate wire definitions. This is a compile error in tools like Verilator. Also code has assign of a wire to itself emitted - probably also an error.

Expected behaviour
Only one copy of wire declared instead of multiple. No assignment of wire to self.

How to reproduce?

cd dup_wires
/usr/local/bin/ghdl synth --std=08 -frelaxed --out=verilog `cat vhdl_files.txt` -e top > top.v
cat top.v | grep const_sr_1_main_c_l114_c10_7dba_return_output 

See duplicate definition of const_sr_1_... wire in output:

$ cat top.v | grep const_sr_1_main_c_l114_c10_7dba_return_output 
  wire [31:0] const_sr_1_main_c_l114_c10_7dba_return_output;
  wire [31:0] const_sr_1_main_c_l114_c10_7dba_return_output;
  assign return_output = const_sr_1_main_c_l114_c10_7dba_return_output;
  assign const_sr_1_main_c_l114_c10_7dba_return_output = const_sr_1_main_c_l114_c10_7dba_return_output; // (signal)
    .return_output(const_sr_1_main_c_l114_c10_7dba_return_output));

Context

GHDL 4.0.0-dev (3.0.0.r448.g2245a7fd1) [Dunoon edition]

Verilator 5.015 devel rev v5.014-50-g5b7e32581

dup_wires.zip

Thank you again for your time!

[tgingold]

Yes, I think this is a known issue. I need to write a pass to distinguish those duplicated names.