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cover fails in output port #2568
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I am not sure what is expected here. The signals are not assigned. |
My colleagues don't like my habit of always finding corner cases ;) I would expect them to behave identically. And both should keep waiting for cover until cycle 12. There is also something weird going on: If I add attribute keep to b
And look the cover_b waveform generated by symbiyosys, b is always '0', even when cover requests it to be high. If I add an assume that b is always '1', the generated cover waveform shows b as '0'. GHDL seems to be synthesizing $cover which is met on arbitrary case. |
Valid use case: A cover to check that the output port can transition. This would be to find forgotten assignments. |
Covering an output is OK, but I am not sure what covering an undefined signal means. |
I understand. Do you agree that both a and b should give the same cover result? |
I passed test.vhdl through yosys:
For me it looks like the first cover is trying to cover a hallucinated wire? And neither of the covers have anything left of 13 cycles. I probably mis-used yosys.
|
You can see the non-optimized, original netlist by using (as a command, not within yosys):
But as both Note that |
Description
The same cover between signal and port behave differently. Test file with out port "a" and signal "b". Both have identical cover.
Using image: hdlc/formal:all
SBY 13:37:55 [test_cover] summary: engine_0 (smtbmc) returned pass
SBY 13:37:55 [test_cover] summary: cover trace: test_cover/engine_0/trace0.vcd
SBY 13:37:55 [test_cover] summary: reached cover statement test.cover_a at in step 0
SBY 13:37:55 [test_cover] summary: cover trace: test_cover/engine_0/trace1.vcd
SBY 13:37:55 [test_cover] summary: reached cover statement test.cover_b at in step 12
Expected behaviour
cover_a and cover_b results should be identical.
How to reproduce?
sby --yosys "yosys -m ghdl" -f test.sby cover
Context
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GHDL Bug occurred
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