DDR instead of LVDS output.

[xolod79]

Hello Sameer! Great project.
I would like to propose adding to the project an option for working not with LVDS outputs, but with regular outputs in DDR mode. I came across two different FPGA boards with the HDMI connector connected to the wrong differential pair outputs. Because of this, ALTLVDS_TX cannot be used.
I was able to transfer serializer.sv to altddio_out. The work has been tested on Cyclone 10LP and MAX10.
I think this approach can also be used with the Lattice FPGA.
But the module requires output of all eight TMDS signals, and not four as now.

[xolod79]

serializer.sv

module serializer
#(
    parameter int NUM_CHANNELS = 3,
    parameter real VIDEO_RATE
)
(
    input logic clk_pixel,
    input logic clk_pixel_x5,
    input logic reset,
    input logic [9:0] tmds_internal [NUM_CHANNELS-1:0],
    output logic [7:0] tmds
);

reg [2:0] TMDS_mod5=0;  // modulus 5 counter
reg [4:0] TMDS_shift_bh=0, TMDS_shift_bl=0;
reg [4:0] TMDS_shift_gh=0, TMDS_shift_gl=0;
reg [4:0] TMDS_shift_rh=0, TMDS_shift_rl=0;

wire [4:0] TMDS_blue_l  = {tmds_internal[0][9],tmds_internal[0][7],tmds_internal[0][5],tmds_internal[0][3],tmds_internal[0][1]};
wire [4:0] TMDS_blue_h  = {tmds_internal[0][8],tmds_internal[0][6],tmds_internal[0][4],tmds_internal[0][2],tmds_internal[0][0]};
wire [4:0] TMDS_green_l = {tmds_internal[1][9],tmds_internal[1][7],tmds_internal[1][5],tmds_internal[1][3],tmds_internal[1][1]};
wire [4:0] TMDS_green_h = {tmds_internal[1][8],tmds_internal[1][6],tmds_internal[1][4],tmds_internal[1][2],tmds_internal[1][0]};
wire [4:0] TMDS_red_l   = {tmds_internal[2][9],tmds_internal[2][7],tmds_internal[2][5],tmds_internal[2][3],tmds_internal[2][1]};
wire [4:0] TMDS_red_h   = {tmds_internal[2][8],tmds_internal[2][6],tmds_internal[2][4],tmds_internal[2][2],tmds_internal[2][0]};

always @(posedge clk_pixel_x5)
begin
   TMDS_shift_bh <= TMDS_mod5[2] ? TMDS_blue_h  : TMDS_shift_bh[4:1];
   TMDS_shift_bl <= TMDS_mod5[2] ? TMDS_blue_l  : TMDS_shift_bl[4:1];
   TMDS_shift_gh <= TMDS_mod5[2] ? TMDS_green_h : TMDS_shift_gh[4:1];
   TMDS_shift_gl <= TMDS_mod5[2] ? TMDS_green_l : TMDS_shift_gl[4:1];
   TMDS_shift_rh <= TMDS_mod5[2] ? TMDS_red_h   : TMDS_shift_rh[4:1];
   TMDS_shift_rl <= TMDS_mod5[2] ? TMDS_red_l   : TMDS_shift_rl[4:1];
   TMDS_mod5     <= TMDS_mod5[2] ? 3'd0 : TMDS_mod5+3'd1;
end

altddio_out1 u_ddio0( .datain_h(~clk_pxl),   .datain_l(~clk_pxl),   .outclock(clk_hdmi), .dataout( tmds[0] ) );
altddio_out1 u_ddio1( .datain_h( clk_pxl),   .datain_l( clk_pxl),   .outclock(clk_hdmi), .dataout( tmds[1] ) );
altddio_out1 u_ddio2( .datain_h(~TMDS_shift_bh[0]), .datain_l(~TMDS_shift_bl[0]), .outclock(clk_hdmi), .dataout( tmds[2] ) );
altddio_out1 u_ddio3( .datain_h( TMDS_shift_bh[0]), .datain_l( TMDS_shift_bl[0]), .outclock(clk_hdmi), .dataout( tmds[3] ) );
altddio_out1 u_ddio4( .datain_h(~TMDS_shift_gh[0]), .datain_l(~TMDS_shift_gl[0]), .outclock(clk_hdmi), .dataout( tmds[4] ) );
altddio_out1 u_ddio5( .datain_h( TMDS_shift_gh[0]), .datain_l( TMDS_shift_gl[0]), .outclock(clk_hdmi), .dataout( tmds[5] ) );
altddio_out1 u_ddio6( .datain_h(~TMDS_shift_rh[0]), .datain_l(~TMDS_shift_rl[0]), .outclock(clk_hdmi), .dataout( tmds[6] ) );
altddio_out1 u_ddio7( .datain_h( TMDS_shift_rh[0]), .datain_l( TMDS_shift_rl[0]), .outclock(clk_hdmi), .dataout( tmds[7] ) );

endmodule