Implementation failed with Vivado 2020.2

[githubxup]

I cannot pass Implementation successfully using Vivado 2020.2 because it showed "Failed Timing!" with red text WNS value -13.672, TNS value -2568.891 and TPWS -0.155.
When I opened the project, I was asked to upgrade project and IPs and I did upgrade both.
In the IP Catalog, a User Repository "D:/Olivier/Xilinx_Vitis/Vitis_VM/Shared/sobelfilter.prj 20200708/sol1/impl/ip" was not there so I remove. Is this an required IP?

Here are the part of logs.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
CRITICAL WARNING: [Timing 38-249] Generated clock system_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock clk_out1_system_clk_wiz_1_0.
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
INFO: [Common 17-206] Exiting Vivado at Thu Dec 24 17:22:21 2020...

James