Passing Verilog string parameters with quotes

[meiniKi]

I have fallen into this trap and wonder if this might be a helpful change:

If a Verilog string parameter is passed in the fusesoc core file with quotation marks, e.g.,

parameters: [CHUNKSIZE=4, RFTYPE="BRAM_DP_BP", ICOBOARD=True]

it gets surrounded by another set of quotes, leading to the following erroneous statement in the edalize_yosys_procs.tcl script

chparam -set RFTYPE {""BRAM_DP_BP""} top_ardutiny}

Suggested change: 45ad9f9 (Is there any loss of generality when stripping unescaped quotation marks?)