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<meta name="description" content="ZYBO Quick-Start Tutorial : Quick-start tutorial for the Digilent ZYBO Zynq-7010 FPGA board using ISE 14/PlanAhead" />
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<h2>Part 3: Peripheral import and ports configuration</h2>
<h3><a name="peripheral-import" class="anchor" href="#peripheral-import"><span class="octicon octicon-link"></span></a>Re-importing the peripheral</h3>
<p>Head back to XPS. (If you accidentally closed it in the meantime, you can open it again from PlanAhead by double-clicking on the <code><strong>your-module</strong>.xmp</code> file in the Sources pane.)</p>
<p>In XPS, select <code>Hardware, Create or Import Peripheral</code> again. Click <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-57.png" title="Xilinx Platform Studio: Peripheral import" />
<p>This time, we chose <code>Import existing peripheral</code> and <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-58.png" title="Import Peripheral: Peripheral flow" />
<p>Like before, select <code>To an XPS project</code>, then click <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-59.png" title="Import Peripheral: Repository or project" />
<p>Select the IP we just edited and click <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-60.png" title="Import Peripheral: Name and version" />
<p>Confirm that we want to overwrite the local design with the changed IP description by clicking <code>Yes</code>.</p>
<img src="images/tutorial-1/tutorial-61.png" title="Overwrite Existing Peripheral" />
<p>Check <code>HDL sources files</code> and click <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-62.png" title="Import Peripheral: Source File Types" />
<p>After that we are presented with two ways to select the HDL source files. If you are not able to import the files from ISE (option 1), select the PAO approach (option 2).</p>
<h4><a name="peripheral-import-xst" class="anchor" href="#peripheral-import-xst"><span class="octicon octicon-link"></span></a>Option 1: Importing the XST project file</h3>
<p>Select <code>Use an XST project file</code> and click <code>Browse</code>.</p>
<img src="images/tutorial-1/tutorial-63.png" title="Import Peripheral: HDL Source Files" />
<p>Navigate to the IP's <code>devl/projnav</code> directory and open the <code><strong>your-ip</strong>.prj</code> from there.</p>
<img src="images/tutorial-1/tutorial-64.png" title="Import Peripheral: Select XST Project File" />
<p>Click <code>Next</code> on the import dialog and confirm that these files are to be imported by clicking <code>Next</code> again.</p>
<img src="images/tutorial-1/tutorial-65.png" title="Import Peripheral: HDL Analysis Information" />
<p>If everything works, you will be taken to to the Bus Interfaces dialog. It is possible that the import fails due to errors in your VHDL description. Head back to ISE and fix the error then. Another problem may be that the project file is in a format the importer does not like. This seems to happen sometimes; In this case, simply go back and use option 2, the PAO approach.</p>
<h4><a name="peripheral-import-pao" class="anchor" href="#peripheral-import-pao"><span class="octicon octicon-link"></span></a>Option 2: Importing the PAO project file</h3>
<p>Alternatively if the list of files used has not changed (i.e. like in this case where we only added logic to existing files), we can import an PAO file by selecting <code>Use existing Peripheral Analysis Order file</code> and clicking <code>Browse</code>.</p>
<img src="images/tutorial-1/tutorial-66.png" title="Import Peripheral: Select XST Project File" />
<p>Select the PAO file in the <code>data</code> directory of the IP.</p>
<img src="images/tutorial-1/tutorial-67.png" title="Import Peripheral: Select PAO file" />
<p>Click <code>Next</code> to import.</p>
<img src="images/tutorial-1/tutorial-68.png" title="Import Peripheral: HDL Source Files" />
<p>The list of files is a bit shorter than with the XST approach. Click <code>Next</code> to accept.</p>
<img src="images/tutorial-1/tutorial-69.png" title="Import Peripheral: HDL Analysis Information" />
<p>Again, if everything works we will be taken to the Bus Interfaces dialog.</p>
<h3><a name="peripheral-import-configure" class="anchor" href="#peripheral-import-configure"><span class="octicon octicon-link"></span></a>IP Configuration</h3>
<p>Since we created an <code>AXI4-Lite</code> peripheral with only <code>Slave</code> functionality, we will select that and confirm using <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-70.png" title="Import Peripheral: Bus Interfaces" />
<p>On the AXI4LITE Port screen nothing needs to be changed, so simply ignore it by clicking <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-71.png" title="Import Peripheral: AXI4LITE Port" />
<p>At the AXI4LITE Parameter screen we need to select the value for the <code>Parameter determine high address</code> field. Select the <code>S_HIGHADDR</code> generic from the dropdown list and continue using <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-72.png" title="Import Peripheral: AXI4LITE Parameter (S_HIGHADDR)" />
<p>On the Parameter Attributes screen we could change our generics, but since we already set a reasonable default in the VHDL file, we can simply skip this window by selecting <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-73.png" title="Import Peripheral: Parameter Attributes" />
<p>Next we can check our ports attributes (i.e. the direction mode, the name, default values etc.). Note that this dialog
has a bug as per ISE Suite 14.7 preventing the displayed parameters to change once a value is selected. This does
not affect the IP itself, so you can safely ignore it.</p>
<p>Click <code>Next</code> to continue.</p>
<img src="images/tutorial-1/tutorial-74.png" title="Import Peripheral: Port Attributes" />
<p>On the final dialog window, select <code>Finish</code> and wait.</p>
<img src="images/tutorial-1/tutorial-75.png" title="Import Peripheral: Finish Line" />
<h3><a name="update-ip-status" class="anchor" href="#update-ip-status"><span class="octicon octicon-link"></span></a>Update IP status</h3>
<p>Looking at the IP Catalog you will notice that the currently imported IP is now marked as <code>PRODUCTION</code>. In that status, the IP will only be synthesized once (i.e. a first time) and
wont ever update again, no matter how many changes you apply to the sources files. In order to continue developing on it, we'll need to change it back to <code>DEVELOPMENT</code>.</p>
<img src="images/tutorial-1/tutorial-76.png" title="Xilinx Platform Studio: IP Catalog: PRODUCTION" />
<p>Right-click it in the catalog and select <code>View MPD</code>.</p>
<img src="images/tutorial-1/tutorial-77.png" title="Xilinx Platform Studio: IP Catalog: View MPD" />
<p>You will notice that the <code>ARCH_SUPPORT_MAP</code> line is missing. In case you didn't write it down, it was:</p>
<p><pre><code>OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)</code></pre></p>
<p>Re-add it to the file, then select <code>Project, Rescan User Repository</code> to force XPS to re-read it.</p>
<img src="images/tutorial-1/tutorial-78.png" title="Xilinx Platform Studio: Rescan User Repositories" />
<p>You will find that the IP is now marked as <code>DEVELOPMENT</code>.</p>
<img src="images/tutorial-1/tutorial-79.png" title="Xilinx Platform Studio: IP Catalog: DEVELOPMENT" />
<p>The import procedure should only be necessary when the public interface of the IP changes, i.e. when changes to the IP wrapper file are made, or if additional files are added.</p>
<h3><a name="configure-ports" class="anchor" href="#configure-ports"><span class="octicon octicon-link"></span></a>Configuring the IP ports</h3>
<p>Head to the <code>Ports</code> tab of the System Assembly View. You will see that the re-imported IP now lists the two inputs and one output we defined, and that they are currently unconnected. Note that the Range field matches the number of connections we defined in the generic parameter, <code>C_NUM_LEDS</code>.</p>
<img src="images/tutorial-1/tutorial-80.png" title="Xilinx Platform Studio: Ports tab" />
<p>In order to wire these signals to physical pins, we need to convert them to external connections. Right-click the entries and select <code>Make External</code>.</p>
<img src="images/tutorial-1/tutorial-81.png" title="Xilinx Platform Studio: Make external" />
<p>After that, they are listed as <code>External Ports</code> with default names based on the signals names and the IP name.</p>
<img src="images/tutorial-1/tutorial-82.png" title="Xilinx Platform Studio: Ports made external" />
<p>Keep note of these port names (or change them by single-clicking on them) and then close XPS. Doing so will save your changes.</p>
<h3>
<a name="pats" class="anchor" href="#pats"><span class="octicon octicon-link"></span></a>Parts of the tutorial</h3>
<ul>
<li>Previous: <a href="part-02.html" title="Setting up a new project" rel="follow,prev">Editing the IP logic.</a></li>
<li>Next: <a href="part-04.html" title="Synthesizing and creating the Bitstream" rel="follow,next">Synthesizing and creating the Bitstream.</a></li>
</ul>
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