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<meta name="description" content="ZYBO Quick-Start Tutorial : Quick-start tutorial for the Digilent ZYBO Zynq-7010 FPGA board using ISE 14/PlanAhead" />
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<h2>Part 4: Synthesizing and creating the Bitstream</h2>
<h3><a name="top-level-and-ucf" class="anchor" href="#top-level-and-ucf"><span class="octicon octicon-link"></span></a>Creating the top-level wrapper and adding user constraints</h3>
<p>Head back to PlanAhead, which will now be available again. Note that in the <code>Sources</code> pane you will find a new file, <code><strong>your-module</strong>.xmp</code>. This is the system definition
we just edited and you might double-click that at any time to head back to XPS.</p>
<img src="images/tutorial-1/tutorial-83.png" title="PlanAhead: Project Sources: XMP File" />
<p>Right-click the XMP file and select <code>Create Top HDL</code> to let PlanAhead generate another wrapper file for you. This will be the main HDL file that instantiates all the PCores added to the design. Think of it as the construction root in a regular software project.</p>
<img src="images/tutorial-1/tutorial-84.png" title="PlanAhead: Project Sources: Create Top HDL" />
<p>After a while, the file should be created and be listed above your XMP module. In case anything goes wrong, simply delete that item and re-create the wrapper again. Deleting it will not delete the XMP file even if it looks that way. Double-click it to open the wrapper HDL file. You will see that the external port names are listed in this file as well. If they are not, try re-importing the IP in XPS and create a new wrapper.</p>
<img src="images/tutorial-1/tutorial-85.png" title="PlanAhead: Project Sources: Top HDL stub" />
<p>Now we will add user constraints to the design that maps signals to actual pins. This step is not required until after the actual synthesis, but we can as well do this right now.</p>
<p>To do so, click <code>Add Sources</code> again in the Project Manager section of the Flow Navigator</p>
<img src="images/tutorial-1/tutorial-86.png" title="PlanAhead: Add Sources" />
<p>This time, select <code>Add or Create Constraints</code> and click <code>Next</code>.</p>
<img src="images/tutorial-1/tutorial-87.png" title="PlanAhead: Add or Create Constraints" />
<p>Download the <code>ZYBO_Master.ucf</code> for ISE designs from Digilent. Click <code>Add Files...</code> and browse to it.</p>
<img src="images/tutorial-1/tutorial-88.png" title="Add Sources: Add or Create Constraints: Add Files" />
<p>The file will now be listed in the dialog. Check <code>Copy constraints files into project</code> to keep the original UCF file and select <code>Finish</code> to return to PlanAhead.</code></p>
<img src="images/tutorial-1/tutorial-89.png" title="Add Sources: Add or Create Constraints: Copy ZYBO Master UCF" />
<p>In the <code>Sources</code> pane you will find a new entry, <code>constrs_1</code> in the <code>Constraints</code> tree. Double-click the UCF file to open it.</p>
<img src="images/tutorial-1/tutorial-90.png" title="PlanAhead: ZYBO Master UCF" />
<p>As you can see from the file name, this file has been copied to <code><strong>your-project</strong>.srcs/constrs_1/imports/xilinx</code> of your project directory.</p>
<img src="images/tutorial-1/tutorial-91.png" title="PlanAhead: UCF location" />
<p>Within the editor, uncomment all the <code>sw<..></code>, <code>btn<..></code> and <code>led<..></code> lines. The number of constrained pins should match the number of your signals,
so this effectively is where your <code>C_NUM_LEDS</code> generic comes into play.</p>
<img src="images/tutorial-1/tutorial-92.png" title="PlanAhead: Edit UCF" />
<p>Rename the net entries according to the signal names you gave in XPS. In case you didn't write them down, simply open the top-level HDL file again to find them.</p>
<p>In this tutorial, they are called <code>ledbtnsw_0_Switches_pin</code>, <code>ledbtnsw_0_Buttons_pin</code> and <code>ledbtnsw_0_LEDs_pin</code>.</p>
<img src="images/tutorial-1/tutorial-93.png" title="PlanAhead: Set internal pin names" />
<h3><a name="synthesis" class="anchor" href="#synthesis"><span class="octicon octicon-link"></span></a>Synthesizing the design</h3>
<p>Now it is time to synthesize the design. In the Synthesis section of the Flow Navigator, select <code>Run Synthesis</code>.</p>
<img src="images/tutorial-1/tutorial-94.png" title="PlanAhead: Synthesize" />
<p>A wait window will appear to show that synthesis has started, but don't get too excited when you see it disappear.</code></p>
<img src="images/tutorial-1/tutorial-95.png" title="PlanAhead: Starting Synthesis" />
<p>In the upper right of PlanAhead you will now find a smaller progress bar reading <code>Running XST</code>. This is the actual synthesis process.</p>
<img src="images/tutorial-1/tutorial-96.png" title="PlanAhead: Running XST" />
<p>After a while, the Synthesis Completed dialog pops up. Select <code>Run Implementation</code> to start the implementation stage, which leads to the place & route process.</p>
<p>If you had not entered the user constraints before, now would be the time to do so before continuing, or otherwise the implementation will fail.</p>
<img src="images/tutorial-1/tutorial-97.png" title="PlanAhead: Synthesis completed" />
<h3><a name="implementation" class="anchor" href="#implementation"><span class="octicon octicon-link"></span></a>Implementing the design</h3>
<p>Again, a progress dialog appears.</p>
<img src="images/tutorial-1/tutorial-98.png" title="PlanAhead: Starting implementation" />
<p>As you can see, the user constraints are processed here.</p>
<img src="images/tutorial-1/tutorial-99.png" title="PlanAhead: Reading and processing constraints" />
<p>You may be confronted with three "Critical Messages" about the PS7 instance that turn out to be entirely uncritical to us. These
non-warnings appear on both the ZYBO and the ZedBoard and I can not explain their cause, but since ignoring them doesn't
seem to do any harm - just click <code>OK</code>.</p>
<img src="images/tutorial-1/tutorial-100.png" title="PlanAhead: Launch Run Critical Messages" />
<p>Again, the dialog disappears just to leave us with the smaller progress bar in the upper right. You'll find <code>Running NGDBuild</code> ...</p>
<img src="images/tutorial-1/tutorial-101.png" title="PlanAhead: Running NGDBuild" />
<p>... <code>Running MAP</code> ...</p>
<img src="images/tutorial-1/tutorial-102.png" title="PlanAhead: Running MAP" />
<p>... <code>Running PAR</code> — which is the place and route process — ...</p>
<img src="images/tutorial-1/tutorial-103.png" title="PlanAhead: Running PAR" />
<p>... <code>Running TRCE</code> ...</p>
<img src="images/tutorial-1/tutorial-104.png" title="PlanAhead: Running TRCE" />
<p>... and <code>Running XDL</code>.</p>
<img src="images/tutorial-1/tutorial-105.png" title="PlanAhead: Running XDL" />
<p>After that, the implementation is complete and we can now generate the bitstream, which is the required end result to configure the programmable logic, much like an executable file for the processing system.</p>
<p>To do so, select <code>Generate Bitstream</code>.</p>
<img src="images/tutorial-1/tutorial-106.png" title="PlanAhead: Implementation Completed" />
<h3><a name="bitstream" class="anchor" href="#bitstream"><span class="octicon octicon-link"></span></a>Creating the Bitstream</h3>
<p>If we had not clicked <code>Generate Bitstream</code> in the last dialog window but instead canceled it, we would chose the <code>Generate Bitstream</code> action under the Program and Debug section in the Flow Navigator now.</p>
<p>Since we did chose it, however, we find the message <code>Running Bitgen</code> in the top right status bar.</p>
<img src="images/tutorial-1/tutorial-107.png" title="PlanAhead: Running Bitgen" />
<p>After a short while the "Bitstream Generation Completed" dialog appears where we chose to open the implemented design.</p>
<img src="images/tutorial-1/tutorial-108.png" title="PlanAhead: Bitstream Generation Completed" />
<p>While we do not need the information at the moment, this will be a required step when exporting the hardware to the
SDK. We can do that now using the <code>File, Export, Export Hardware for SDK</code> menu.</p>
<img src="images/tutorial-1/tutorial-109.png" title="PlanAhead: Export Hardware for SDK" />
<p>In the upcoming dialog, among <code>Export Hardware</code> and <code>Launch SDK</code>, select <code>Include bitstream</code>. If this option is greyed out, press Cancel and select
<code>Open Implemented Design</code> in the Implementation section of the Flow Navigator pane, then export again.</p>
<p>This is also a quick way to re-launch SDK should you need to do so.</p>
<img src="images/tutorial-1/tutorial-120.png" title="Export Hardware for SDK" />
<p>After that, you might <a href="part-05.html" title="Programming the Processing System" rel="follow,next">skip to the next part</a> or read on if you are interested.</p>
<h3><a name="using-impact" class="anchor" href="#using-impact"><span class="octicon octicon-link"></span></a>Optional: Programming the FPGA using iMPACT</h3>
<p>Alternatively to using the SDK — or in addition to it — the FPGA can be configured (i.e. "programmed") right now using Xilinx iMPACT. We can do so by clicking <code>Launch iMPACT</code> in the Program and Debug section.</p>
<p>Note that generally the Zynq AP SoCs are bootstrapped by the ARM core, much like a regular microcontroller system where the FPGA acts as a slave during startup. That means that generally using the FPGA logic will only work after the FPGA has been initialized by the ARM core, i.e. when the ARM core is already flashed with a program that initializes the FPGA. When using iMPACT to configure the FPGA on the fly, this restriction does not apply.<p>
<img src="images/tutorial-1/tutorial-110.png" title="PlanAhead: Launch iMPACT" />
<p>If you happen to have the <strong>Digilent Adept</strong> suite and the <strong>Digilent Plugins for Xilinx Tools</strong> installed <emph>and</emph> your cable driver configured, you may see a window like the following. You <strong>will</strong> need both Adept and the plugins along the way, so download and install them now if they are still missing.</p>
<img src="images/tutorial-1/tutorial-111.png" title="iMPACT: Boundary Scan" />
<p>If you find an empty window or want to make sure everything is correct, check your cable setup by selecting <code>Output, Cable Setup...</code>.</p>
<img src="images/tutorial-1/tutorial-112.png" title="iMPACT: Cable Setup" />
<p>In the following dialog select the <code>Digilent USB JTAG Cable</code> option (available after installing Adept and the Digilent Plugins) and select your board in the <code>Port</code> dropdown. Close the dialog, accepting the changes.</p>
<p>Should the cable option appear and the Port dropdown remain empty, make sure you really installed the latest version of Adept.</p>
<img src="images/tutorial-1/tutorial-113.png" title="iMPACT: Cable Communication Setup" />
<p>In the <code>Boundary Scan</code> flow, both the ARM core and the FPGA should be detected now. Right-click the FPGA
and select <code>Set Target Device</code> to feel good.</p>
<img src="images/tutorial-1/tutorial-114.png" title="iMPACT: Setting the target device" />
<p>Next, by right-clicking the FPGA again, select <code>Program</code>.</p>
<img src="images/tutorial-1/tutorial-115.png" title="iMPACT: Program" />
<p>In the Device Programming Properties dialog that pops up, just click <code>OK</code>.</p>
<img src="images/tutorial-1/tutorial-116.png" title="iMPACT: Device Programming Properties" />
<p>After a short while, the FPGA should be programmed and already responding to your inputs. Try fiddling with the switches and buttons to see if it works. If it does not, make sure the ARM core is initialized first and/or move on to the SDK.</p>
<img src="images/tutorial-1/tutorial-117.png" title="iMPACT: Program Succeeded" />
<p>After that, close iMPACT and export the hardware for the SDK for profit and cake.</p>
<img src="images/tutorial-1/tutorial-119.png" title="iMPACT: Program Succeeded" />
<p>You may ignore the save dialog, as your changes here will be remembered anyway.</p>
<h3>
<a name="pats" class="anchor" href="#pats"><span class="octicon octicon-link"></span></a>Parts of the tutorial</h3>
<ul>
<li>Previous: <a href="part-03.html" title="Peripheral import and ports configuration" rel="follow,prev">Peripheral import and ports configuration.</a></li>
<li>Next: <a href="part-05.html" title="Programming the Processing System" rel="follow,next">Programming the Processing System.</a></li>
</ul>
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