Code generation tool for control and status registers
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Updated
Jun 11, 2024 - Ruby
Code generation tool for control and status registers
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Common SystemVerilog RTL modules for RgGen
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
Реализация AXI интерфейса на SystemVerilog
A comprehensive MERN stack project for online learning, connecting students with teachers, enabling class management, assignments, and seamless admin oversight.
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
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