Image Processing Toolbox in Verilog using Basys3 FPGA
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Updated
Sep 19, 2023 - VHDL
Image Processing Toolbox in Verilog using Basys3 FPGA
This repository has basic examples in VHDL using Basys3 board.
A Single Cycle Risc-V 32 bit CPU
Term project for CS223 Digital - Design course.
Color Detection using Basys3 FPGA
EE89H Final Project
Complex Adder with Seven Segment Display
Digital Clock for the Basys 3 FPGA
Multi-application FPGA project built with Verilog
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
Xilinx Vivado project for nanoprocessor designing with VHDL
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