TURBOdeb #xohw19-157 #TuringBombe #Enigma
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Updated
Nov 9, 2019 - Coq
TURBOdeb #xohw19-157 #TuringBombe #Enigma
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Predicting 3D human pose from single image using a VCK5000 Versal Development Card
Develop DMA acceleration of the system that performs linear computing functions, Y = AX + B, large amounts of data.
Janus astrophysics Simulator implemented on ZU19EG Ultrascale+
A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.
University of Pittsburgh ECE 1195
Smart Automation Controller for Precision Agriculture
Blake2 RTL implementation
An FPGA design for simulating biological neurons
Janus Algorithm in C++ version without FPGA acceleration.
Projekt zaliczeniowy w ramach przedmiotu "Systemy Cyfrowe". Projekt miał na celu stworzenie układu DSP do pomiaru odległości za pomocą odbitego światła lasera. Wykonano układ który można finalnie uruchomić na płytce Cyclone IV Altera (model EP4CE6E22), który można sterować bezpośrednio na płytce. Objaśnienie projektu znajduje się w załączonym do…
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS
FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.
A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.
FPGA with Xilinx Vitis HLS and ZYNQ board. AXI and VHDL: Simple Multiplier, AXI and VHDL: DoGain
Implementation of a somewhat homomorphic encryption system using an FPGA hardware accelerator. This project was part of my bachelor's thesis at KIT and developed in four months.
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