An FPGA design for simulating biological neurons
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Updated
Jun 2, 2024 - SystemVerilog
An FPGA design for simulating biological neurons
Research and Materials on Hardware implementation of Transformer Model
OpenGL 1.x implementation for FPGAs
QKeras: a quantization deep learning library for Tensorflow Keras
A heterogeneous implementation (SW/HW) of an image processing algorithm running on a Yocto-linux OS
A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
📈 Welcome to the repository that powers the future of stock market analysis with lightning-fast hardware acceleration on FPGA! ⚡️
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.
Implementation of a somewhat homomorphic encryption system using an FPGA hardware accelerator. This project was part of my bachelor's thesis at KIT and developed in four months.
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.
The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"
Blake2 RTL implementation
Projekt zaliczeniowy w ramach przedmiotu "Systemy Cyfrowe". Projekt miał na celu stworzenie układu DSP do pomiaru odległości za pomocą odbitego światła lasera. Wykonano układ który można finalnie uruchomić na płytce Cyclone IV Altera (model EP4CE6E22), który można sterować bezpośrednio na płytce. Objaśnienie projektu znajduje się w załączonym do…
University of Pittsburgh ECE 1195
Convolutional accelerator kernel, target ASIC & FPGA
Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.
Reconfigurable Digital Systems HRY591-project.
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