NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA
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Updated
Oct 10, 2022 - Verilog
NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA
Draft repository for Digital Computer Design @ MMU
PongFPGA: Experience the classic Pong game reimagined with FPGA tech! 🕹️ Dive into the world of hardware programming for thrilling entertainment and education! 🚀🎮
This is a template for projects using the Quartus Prime suite with the DE10-Lite FPGA board.
Verilog code developed for the Altera Cyclone II EP2C5
Coursework for ELEC60011: Digital System Design - a Quartus project containing a NIOS II soft-core and custom instruction hardware accelerators for the target function
Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.
Simple test for interfacing FPGA and SoC on a de10 nano board
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
100×60 text mode in 800×600 @ 72 Hz on a DE0 Nano SoC without special hardware
Tamagotchi Implementation in VHDL
EV21 RISC Processor Design
Introductory guide to building and programming FPGAs
This is a very basic replication of the popular rhythm / platformer game Geometry Dash, implemented completely in hardware through System Verilog
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
Used Verilog HDL modules in Quartus Prime Software to simulate a machine learning processor on an FPGA board. UART protocol was used for used input.
UART Transmitter and Receiver implementation for FPGA
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