NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA
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Updated
Oct 10, 2022 - Verilog
NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA
The open 4-bit system for Altera DE2 drawn and compiled with Quartus
Draft repository for Digital Computer Design @ MMU
PongFPGA: Experience the classic Pong game reimagined with FPGA tech! 🕹️ Dive into the world of hardware programming for thrilling entertainment and education! 🚀🎮
Verilog code developed for the Altera Cyclone II EP2C5
Coursework for ELEC60011: Digital System Design - a Quartus project containing a NIOS II soft-core and custom instruction hardware accelerators for the target function
100×60 text mode in 800×600 @ 72 Hz on a DE0 Nano SoC without special hardware
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.
Tutorial para criação de projetos no Quartus Prime Lite Editon.
Microprocessor design with Quartus by using Verilog Programming.
This is a very basic replication of the popular rhythm / platformer game Geometry Dash, implemented completely in hardware through System Verilog
FPGA stuff
EE-309 Course Project - 2
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
Max Destil's Advanced VLSI Design course project portfolio. See link for course description.
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