rtl
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A sample of online academic CV in English and Persian
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Jun 11, 2024 - JavaScript
This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.
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Jun 11, 2024 - SystemVerilog
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Jun 11, 2024 - Scala
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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Jun 11, 2024 - C
VeeR EL2 Core
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Jun 11, 2024 - SystemVerilog
Verilator open-source SystemVerilog simulator and lint system
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Jun 11, 2024 - C++
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Jun 11, 2024 - Verilog
Code generation tool for control and status registers
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Jun 11, 2024 - Ruby
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Jun 11, 2024 - Verilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
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Jun 11, 2024 - SystemVerilog
Veryl: A Modern Hardware Description Language
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Jun 11, 2024 - Rust
Free, open-source, and cross-platform analysis tool for Scrabble, Super Scrabble & Literaki. Quickly find top scoring words using given letters and board state. Available in English, French, German, Persian, Polish, Romanian & Spanish.
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Jun 10, 2024 - TypeScript
23년 안에 배포, 24년엔 리팩토링
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Jun 11, 2024 - TypeScript
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
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Jun 11, 2024 - Verilog
PostCSS plugin to automatically build Cascading Style Sheets (CSS) with Left-To-Right (LTR) and Right-To-Left (RTL) rules using RTLCSS
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Jun 9, 2024 - TypeScript
Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)
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Jun 9, 2024 - Bluespec
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