verilator
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A single cycle processor implementing a subset of the ARMv7 ISA.
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Sep 11, 2018 - SystemVerilog
Verilator Testbench Environment
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Mar 6, 2019 - C++
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
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Mar 6, 2019 - Verilog
SystemC UVM environment generator for PyGears components. RTL simulated with Verilator
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Oct 13, 2019 - C++
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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Nov 25, 2019 - SystemVerilog
A ZipCPU SoC for the Nexys Video board supporting video functionality
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Dec 20, 2019 - Verilog
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