intel_pxp.c

/* SPDX-License-Identifier: MIT */
/*
 * Copyright(c) 2020 Intel Corporation.
 */

#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"

int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file *drmfile)
{
	int ret;
	struct pxp_info pxp_info = {0};
	struct drm_i915_pxp_ops *pxp_ops = data;
	struct drm_i915_private *i915 = to_i915(dev);

	drm_dbg(&i915->drm, ">>> %s\n", __func__);

	if (!i915 || !drmfile || !pxp_ops || pxp_ops->pxp_info_size != sizeof(pxp_info)) {
		drm_dbg(&i915->drm, "Failed to %s, invalid params\n", __func__);
		ret = -EINVAL;
		goto end;
	}

	if (copy_from_user(&pxp_info, (void __user *)pxp_ops->pxp_info_ptr, sizeof(pxp_info)) != 0) {
		ret = -EFAULT;
		goto end;
	}

	drm_dbg(&i915->drm, "i915 pxp ioctl call with action=[%d]\n", pxp_info.action);

	mutex_lock(&i915->pxp.r0ctx->ctx_mutex);

	if (i915->pxp.r0ctx->global_state_in_suspend) {
		drm_dbg(&i915->drm, "Return failure due to state in suspend\n");
		pxp_info.sm_status = PXP_SM_STATUS_SESSION_NOT_AVAILABLE;
		ret = 0;
		goto end;
	}

	if (i915->pxp.r0ctx->global_state_attacked) {
		drm_dbg(&i915->drm, "Retry required due to state attacked\n");
		pxp_info.sm_status = PXP_SM_STATUS_RETRY_REQUIRED;
		ret = 0;
		goto end;
	}

	switch (pxp_info.action) {
	case PXP_ACTION_SET_R3_CONTEXT:
	{
		ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
		break;
	}
	default:
		drm_dbg(&i915->drm, "Failed to %s due to bad params\n", __func__);
		ret = -EINVAL;
		goto end;
	}

end:
	mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);

	if (ret == 0)
		if (copy_to_user((void __user *)pxp_ops->pxp_info_ptr, &pxp_info, sizeof(pxp_info)) != 0)
			ret = -EFAULT;

	if (ret)
		dev_err(&dev->pdev->dev, "pid=%d, ret = %d\n", task_pid_nr(current), ret);

	drm_dbg(&i915->drm, "<<< %s\n", __func__);
	return ret;
}

static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
{
	WARN_ON(INTEL_GEN(i915) < 11);

	/* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
	intel_uncore_write(&i915->uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask << 16);
}

static void intel_pxp_unmask_irq(struct intel_gt *gt)
{
	lockdep_assert_held(&gt->irq_lock);

	intel_pxp_write_irq_mask_reg(gt->i915, 0);
}

static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
{
	lockdep_assert_held(&gt->irq_lock);

	intel_pxp_write_irq_mask_reg(gt->i915, mask);
}

static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
{
	drm_dbg(&i915->drm, "%s was called\n", __func__);

	mutex_lock(&i915->pxp.r0ctx->ctx_mutex);

	i915->pxp.r0ctx->global_state_attacked = true;
	i915->pxp.r0ctx->flag_display_hm_surface_keys = false;

	intel_pxp_destroy_r3ctx_list(i915);

	mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);

	return 0;
}

static int intel_pxp_global_terminate_complete_callback(struct drm_i915_private *i915)
{
	int ret = 0;

	drm_dbg(&i915->drm, ">>> %s\n", __func__);

	mutex_lock(&i915->pxp.r0ctx->ctx_mutex);

	if (i915->pxp.r0ctx->global_state_attacked)
		i915->pxp.r0ctx->global_state_attacked = false;

	mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);

	drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);

	return ret;
}

static void intel_pxp_irq_work(struct work_struct *work)
{
	struct intel_pxp *pxp_ptr = container_of(work, typeof(*pxp_ptr), irq_work);
	struct drm_i915_private *i915 = container_of(pxp_ptr, typeof(*i915), pxp);
	u32 events = 0;

	spin_lock_irq(&i915->gt.irq_lock);
	events = fetch_and_zero(&pxp_ptr->current_events);
	spin_unlock_irq(&i915->gt.irq_lock);

	drm_dbg(&i915->drm, "%s was called with events=[%d]\n", __func__, events);

	if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
	    events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
		intel_pxp_teardown_required_callback(i915);

	if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
		intel_pxp_global_terminate_complete_callback(i915);

	spin_lock_irq(&i915->gt.irq_lock);
	intel_pxp_unmask_irq(&i915->gt);
	spin_unlock_irq(&i915->gt.irq_lock);
}

int intel_pxp_init(struct drm_i915_private *i915)
{
	int ret;

	drm_info(&i915->drm, "i915_pxp_init\n");

	i915->pxp.r0ctx = intel_pxp_create_r0ctx(i915);
	if (!i915->pxp.r0ctx) {
		drm_dbg(&i915->drm, "Failed to create pxp ctx\n");
		return -EFAULT;
	}

	ret = pxp_sm_set_kcr_init_reg(i915);
	if (ret) {
		drm_dbg(&i915->drm, "Failed to set kcr init reg\n");
		return ret;
	}

	INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);

	i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
				 PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
				 PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);

	return ret;
}

void intel_pxp_uninit(struct drm_i915_private *i915)
{
	intel_pxp_destroy_r0ctx(i915);
}

/**
 * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
 * @gt: valid GT instance
 * @iir: GT interrupt vector associated with the interrupt
 *
 * Dispatches each vector element into an IRQ to PXP.
 */
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
{
	struct drm_i915_private *i915 = gt->i915;
	const u32 events = iir & i915->pxp.handled_irr;

	drm_dbg(&i915->drm, "%s was called with iir=[0x%04x]\n", __func__, iir);

	lockdep_assert_held(&gt->irq_lock);

	if (unlikely(!events)) {
		drm_dbg(&i915->drm, "%s returned due to iir=[0x%04x]\n", __func__, iir);
		goto end;
	}

	intel_pxp_mask_irq(gt, i915->pxp.handled_irr);

	i915->pxp.current_events |= events;
	schedule_work(&i915->pxp.irq_work);
end:
	return;
}