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i915_gem_context.c
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i915_gem_context.c
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/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2011-2012 Intel Corporation
*/
/*
* This file implements HW context support. On gen5+ a HW context consists of an
* opaque GPU object which is referenced at times of context saves and restores.
* With RC6 enabled, the context is also referenced as the GPU enters and exists
* from RC6 (GPU has it's own internal power context, except on gen5). Though
* something like a context does exist for the media ring, the code only
* supports contexts for the render ring.
*
* In software, there is a distinction between contexts created by the user,
* and the default HW context. The default HW context is used by GPU clients
* that do not request setup of their own hardware context. The default
* context's state is never restored to help prevent programming errors. This
* would happen if a client ran and piggy-backed off another clients GPU state.
* The default context only exists to give the GPU some offset to load as the
* current to invoke a save of the context we actually care about. In fact, the
* code could likely be constructed, albeit in a more complicated fashion, to
* never use the default context, though that limits the driver's ability to
* swap out, and/or destroy other contexts.
*
* All other contexts are created as a request by the GPU client. These contexts
* store GPU state, and thus allow GPU clients to not re-emit state (and
* potentially query certain state) at any time. The kernel driver makes
* certain that the appropriate commands are inserted.
*
* The context life cycle is semi-complicated in that context BOs may live
* longer than the context itself because of the way the hardware, and object
* tracking works. Below is a very crude representation of the state machine
* describing the context life.
* refcount pincount active
* S0: initial state 0 0 0
* S1: context created 1 0 0
* S2: context is currently running 2 1 X
* S3: GPU referenced, but not current 2 0 1
* S4: context is current, but destroyed 1 1 0
* S5: like S3, but destroyed 1 0 1
*
* The most common (but not all) transitions:
* S0->S1: client creates a context
* S1->S2: client submits execbuf with context
* S2->S3: other clients submits execbuf with context
* S3->S1: context object was retired
* S3->S2: clients submits another execbuf
* S2->S4: context destroy called with current context
* S3->S5->S0: destroy path
* S4->S5->S0: destroy path on current context
*
* There are two confusing terms used above:
* The "current context" means the context which is currently running on the
* GPU. The GPU has loaded its state already and has stored away the gtt
* offset of the BO. The GPU is not actively referencing the data at this
* offset, but it will on the next context switch. The only way to avoid this
* is to do a GPU reset.
*
* An "active context' is one which was previously the "current context" and is
* on the active list waiting for the next context switch to occur. Until this
* happens, the object must remain at the same gtt offset. It is therefore
* possible to destroy a context, but it is still active.
*
*/
#include <linux/log2.h>
#include <linux/nospec.h>
#include <drm/drm_syncobj.h>
#include "gt/gen6_ppgtt.h"
#include "gt/intel_context.h"
#include "gt/intel_context_param.h"
#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_execlists_submission.h" /* virtual_engine */
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
#include "i915_gem_context.h"
#include "i915_globals.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
static struct i915_global_gem_context {
struct i915_global base;
struct kmem_cache *slab_luts;
} global;
struct i915_lut_handle *i915_lut_handle_alloc(void)
{
return kmem_cache_alloc(global.slab_luts, GFP_KERNEL);
}
void i915_lut_handle_free(struct i915_lut_handle *lut)
{
return kmem_cache_free(global.slab_luts, lut);
}
static void lut_close(struct i915_gem_context *ctx)
{
struct radix_tree_iter iter;
void __rcu **slot;
mutex_lock(&ctx->lut_mutex);
rcu_read_lock();
radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
struct i915_vma *vma = rcu_dereference_raw(*slot);
struct drm_i915_gem_object *obj = vma->obj;
struct i915_lut_handle *lut;
if (!kref_get_unless_zero(&obj->base.refcount))
continue;
spin_lock(&obj->lut_lock);
list_for_each_entry(lut, &obj->lut_list, obj_link) {
if (lut->ctx != ctx)
continue;
if (lut->handle != iter.index)
continue;
list_del(&lut->obj_link);
break;
}
spin_unlock(&obj->lut_lock);
if (&lut->obj_link != &obj->lut_list) {
i915_lut_handle_free(lut);
radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
i915_vma_close(vma);
i915_gem_object_put(obj);
}
i915_gem_object_put(obj);
}
rcu_read_unlock();
mutex_unlock(&ctx->lut_mutex);
}
static struct intel_context *
lookup_user_engine(struct i915_gem_context *ctx,
unsigned long flags,
const struct i915_engine_class_instance *ci)
#define LOOKUP_USER_INDEX BIT(0)
{
int idx;
if (!!(flags & LOOKUP_USER_INDEX) != i915_gem_context_user_engines(ctx))
return ERR_PTR(-EINVAL);
if (!i915_gem_context_user_engines(ctx)) {
struct intel_engine_cs *engine;
engine = intel_engine_lookup_user(ctx->i915,
ci->engine_class,
ci->engine_instance);
if (!engine)
return ERR_PTR(-EINVAL);
idx = engine->legacy_idx;
} else {
idx = ci->engine_instance;
}
return i915_gem_context_get_engine(ctx, idx);
}
static int validate_priority(struct drm_i915_private *i915,
const struct drm_i915_gem_context_param *args)
{
s64 priority = args->value;
if (args->size)
return -EINVAL;
if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
return -ENODEV;
if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
priority < I915_CONTEXT_MIN_USER_PRIORITY)
return -EINVAL;
if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
!capable(CAP_SYS_NICE))
return -EPERM;
return 0;
}
static void proto_context_close(struct i915_gem_proto_context *pc)
{
int i;
if (pc->vm)
i915_vm_put(pc->vm);
if (pc->user_engines) {
for (i = 0; i < pc->num_user_engines; i++)
kfree(pc->user_engines[i].siblings);
kfree(pc->user_engines);
}
kfree(pc);
}
static int proto_context_set_persistence(struct drm_i915_private *i915,
struct i915_gem_proto_context *pc,
bool persist)
{
if (persist) {
/*
* Only contexts that are short-lived [that will expire or be
* reset] are allowed to survive past termination. We require
* hangcheck to ensure that the persistent requests are healthy.
*/
if (!i915->params.enable_hangcheck)
return -EINVAL;
pc->user_flags |= BIT(UCONTEXT_PERSISTENCE);
} else {
/* To cancel a context we use "preempt-to-idle" */
if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
return -ENODEV;
/*
* If the cancel fails, we then need to reset, cleanly!
*
* If the per-engine reset fails, all hope is lost! We resort
* to a full GPU reset in that unlikely case, but realistically
* if the engine could not reset, the full reset does not fare
* much better. The damage has been done.
*
* However, if we cannot reset an engine by itself, we cannot
* cleanup a hanging persistent context without causing
* colateral damage, and we should not pretend we can by
* exposing the interface.
*/
if (!intel_has_reset_engine(&i915->gt))
return -ENODEV;
pc->user_flags &= ~BIT(UCONTEXT_PERSISTENCE);
}
return 0;
}
static struct i915_gem_proto_context *
proto_context_create(struct drm_i915_private *i915, unsigned int flags)
{
struct i915_gem_proto_context *pc, *err;
pc = kzalloc(sizeof(*pc), GFP_KERNEL);
if (!pc)
return ERR_PTR(-ENOMEM);
pc->num_user_engines = -1;
pc->user_engines = NULL;
pc->user_flags = BIT(UCONTEXT_BANNABLE) |
BIT(UCONTEXT_RECOVERABLE);
if (i915->params.enable_hangcheck)
pc->user_flags |= BIT(UCONTEXT_PERSISTENCE);
pc->sched.priority = I915_PRIORITY_NORMAL;
if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
if (!HAS_EXECLISTS(i915)) {
err = ERR_PTR(-EINVAL);
goto proto_close;
}
pc->single_timeline = true;
}
return pc;
proto_close:
proto_context_close(pc);
return err;
}
static int proto_context_register_locked(struct drm_i915_file_private *fpriv,
struct i915_gem_proto_context *pc,
u32 *id)
{
int ret;
void *old;
lockdep_assert_held(&fpriv->proto_context_lock);
ret = xa_alloc(&fpriv->context_xa, id, NULL, xa_limit_32b, GFP_KERNEL);
if (ret)
return ret;
old = xa_store(&fpriv->proto_context_xa, *id, pc, GFP_KERNEL);
if (xa_is_err(old)) {
xa_erase(&fpriv->context_xa, *id);
return xa_err(old);
}
WARN_ON(old);
return 0;
}
static int proto_context_register(struct drm_i915_file_private *fpriv,
struct i915_gem_proto_context *pc,
u32 *id)
{
int ret;
mutex_lock(&fpriv->proto_context_lock);
ret = proto_context_register_locked(fpriv, pc, id);
mutex_unlock(&fpriv->proto_context_lock);
return ret;
}
static int set_proto_ctx_vm(struct drm_i915_file_private *fpriv,
struct i915_gem_proto_context *pc,
const struct drm_i915_gem_context_param *args)
{
struct drm_i915_private *i915 = fpriv->dev_priv;
struct i915_address_space *vm;
if (args->size)
return -EINVAL;
if (!HAS_FULL_PPGTT(i915))
return -ENODEV;
if (upper_32_bits(args->value))
return -ENOENT;
vm = i915_gem_vm_lookup(fpriv, args->value);
if (!vm)
return -ENOENT;
if (pc->vm)
i915_vm_put(pc->vm);
pc->vm = vm;
return 0;
}
struct set_proto_ctx_engines {
struct drm_i915_private *i915;
unsigned num_engines;
struct i915_gem_proto_engine *engines;
};
static int
set_proto_ctx_engines_balance(struct i915_user_extension __user *base,
void *data)
{
struct i915_context_engines_load_balance __user *ext =
container_of_user(base, typeof(*ext), base);
const struct set_proto_ctx_engines *set = data;
struct drm_i915_private *i915 = set->i915;
struct intel_engine_cs **siblings;
u16 num_siblings, idx;
unsigned int n;
int err;
if (!HAS_EXECLISTS(i915))
return -ENODEV;
if (intel_uc_uses_guc_submission(&i915->gt.uc))
return -ENODEV; /* not implement yet */
if (get_user(idx, &ext->engine_index))
return -EFAULT;
if (idx >= set->num_engines) {
drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
idx, set->num_engines);
return -EINVAL;
}
idx = array_index_nospec(idx, set->num_engines);
if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_INVALID) {
drm_dbg(&i915->drm,
"Invalid placement[%d], already occupied\n", idx);
return -EEXIST;
}
if (get_user(num_siblings, &ext->num_siblings))
return -EFAULT;
err = check_user_mbz(&ext->flags);
if (err)
return err;
err = check_user_mbz(&ext->mbz64);
if (err)
return err;
if (num_siblings == 0)
return 0;
siblings = kmalloc_array(num_siblings, sizeof(*siblings), GFP_KERNEL);
if (!siblings)
return -ENOMEM;
for (n = 0; n < num_siblings; n++) {
struct i915_engine_class_instance ci;
if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
err = -EFAULT;
goto err_siblings;
}
siblings[n] = intel_engine_lookup_user(i915,
ci.engine_class,
ci.engine_instance);
if (!siblings[n]) {
drm_dbg(&i915->drm,
"Invalid sibling[%d]: { class:%d, inst:%d }\n",
n, ci.engine_class, ci.engine_instance);
err = -EINVAL;
goto err_siblings;
}
}
if (num_siblings == 1) {
set->engines[idx].type = I915_GEM_ENGINE_TYPE_PHYSICAL;
set->engines[idx].engine = siblings[0];
kfree(siblings);
} else {
set->engines[idx].type = I915_GEM_ENGINE_TYPE_BALANCED;
set->engines[idx].num_siblings = num_siblings;
set->engines[idx].siblings = siblings;
}
return 0;
err_siblings:
kfree(siblings);
return err;
}
static int
set_proto_ctx_engines_bond(struct i915_user_extension __user *base, void *data)
{
struct i915_context_engines_bond __user *ext =
container_of_user(base, typeof(*ext), base);
const struct set_proto_ctx_engines *set = data;
struct drm_i915_private *i915 = set->i915;
struct i915_engine_class_instance ci;
struct intel_engine_cs *master;
u16 idx, num_bonds;
int err, n;
if (get_user(idx, &ext->virtual_index))
return -EFAULT;
if (idx >= set->num_engines) {
drm_dbg(&i915->drm,
"Invalid index for virtual engine: %d >= %d\n",
idx, set->num_engines);
return -EINVAL;
}
idx = array_index_nospec(idx, set->num_engines);
if (set->engines[idx].type == I915_GEM_ENGINE_TYPE_INVALID) {
drm_dbg(&i915->drm, "Invalid engine at %d\n", idx);
return -EINVAL;
}
if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_PHYSICAL) {
drm_dbg(&i915->drm,
"Bonding with virtual engines not allowed\n");
return -EINVAL;
}
err = check_user_mbz(&ext->flags);
if (err)
return err;
for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
err = check_user_mbz(&ext->mbz64[n]);
if (err)
return err;
}
if (copy_from_user(&ci, &ext->master, sizeof(ci)))
return -EFAULT;
master = intel_engine_lookup_user(i915,
ci.engine_class,
ci.engine_instance);
if (!master) {
drm_dbg(&i915->drm,
"Unrecognised master engine: { class:%u, instance:%u }\n",
ci.engine_class, ci.engine_instance);
return -EINVAL;
}
if (get_user(num_bonds, &ext->num_bonds))
return -EFAULT;
for (n = 0; n < num_bonds; n++) {
struct intel_engine_cs *bond;
if (copy_from_user(&ci, &ext->engines[n], sizeof(ci)))
return -EFAULT;
bond = intel_engine_lookup_user(i915,
ci.engine_class,
ci.engine_instance);
if (!bond) {
drm_dbg(&i915->drm,
"Unrecognised engine[%d] for bonding: { class:%d, instance: %d }\n",
n, ci.engine_class, ci.engine_instance);
return -EINVAL;
}
}
return 0;
}
static const i915_user_extension_fn set_proto_ctx_engines_extensions[] = {
[I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_proto_ctx_engines_balance,
[I915_CONTEXT_ENGINES_EXT_BOND] = set_proto_ctx_engines_bond,
};
static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv,
struct i915_gem_proto_context *pc,
const struct drm_i915_gem_context_param *args)
{
struct drm_i915_private *i915 = fpriv->dev_priv;
struct set_proto_ctx_engines set = { .i915 = i915 };
struct i915_context_param_engines __user *user =
u64_to_user_ptr(args->value);
unsigned int n;
u64 extensions;
int err;
if (pc->num_user_engines >= 0) {
drm_dbg(&i915->drm, "Cannot set engines twice");
return -EINVAL;
}
if (args->size < sizeof(*user) ||
!IS_ALIGNED(args->size - sizeof(*user), sizeof(*user->engines))) {
drm_dbg(&i915->drm, "Invalid size for engine array: %d\n",
args->size);
return -EINVAL;
}
set.num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines);
/* RING_MASK has no shift so we can use it directly here */
if (set.num_engines > I915_EXEC_RING_MASK + 1)
return -EINVAL;
set.engines = kmalloc_array(set.num_engines, sizeof(*set.engines), GFP_KERNEL);
if (!set.engines)
return -ENOMEM;
for (n = 0; n < set.num_engines; n++) {
struct i915_engine_class_instance ci;
struct intel_engine_cs *engine;
if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) {
kfree(set.engines);
return -EFAULT;
}
memset(&set.engines[n], 0, sizeof(set.engines[n]));
if (ci.engine_class == (u16)I915_ENGINE_CLASS_INVALID &&
ci.engine_instance == (u16)I915_ENGINE_CLASS_INVALID_NONE)
continue;
engine = intel_engine_lookup_user(i915,
ci.engine_class,
ci.engine_instance);
if (!engine) {
drm_dbg(&i915->drm,
"Invalid engine[%d]: { class:%d, instance:%d }\n",
n, ci.engine_class, ci.engine_instance);
kfree(set.engines);
return -ENOENT;
}
set.engines[n].type = I915_GEM_ENGINE_TYPE_PHYSICAL;
set.engines[n].engine = engine;
}
err = -EFAULT;
if (!get_user(extensions, &user->extensions))
err = i915_user_extensions(u64_to_user_ptr(extensions),
set_proto_ctx_engines_extensions,
ARRAY_SIZE(set_proto_ctx_engines_extensions),
&set);
if (err) {
kfree(set.engines);
return err;
}
pc->num_user_engines = set.num_engines;
pc->user_engines = set.engines;
return 0;
}
static int set_proto_ctx_sseu(struct drm_i915_file_private *fpriv,
struct i915_gem_proto_context *pc,
struct drm_i915_gem_context_param *args)
{
struct drm_i915_private *i915 = fpriv->dev_priv;
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_sseu *sseu;
int ret;
if (args->size < sizeof(user_sseu))
return -EINVAL;
if (GRAPHICS_VER(i915) != 11)
return -ENODEV;
if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
sizeof(user_sseu)))
return -EFAULT;
if (user_sseu.rsvd)
return -EINVAL;
if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
return -EINVAL;
if (!!(user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX) != (pc->num_user_engines >= 0))
return -EINVAL;
if (pc->num_user_engines >= 0) {
int idx = user_sseu.engine.engine_instance;
struct i915_gem_proto_engine *pe;
if (idx >= pc->num_user_engines)
return -EINVAL;
pe = &pc->user_engines[idx];
/* Only render engine supports RPCS configuration. */
if (pe->engine->class != RENDER_CLASS)
return -EINVAL;
sseu = &pe->sseu;
} else {
/* Only render engine supports RPCS configuration. */
if (user_sseu.engine.engine_class != I915_ENGINE_CLASS_RENDER)
return -EINVAL;
/* There is only one render engine */
if (user_sseu.engine.engine_instance != 0)
return -EINVAL;
sseu = &pc->legacy_rcs_sseu;
}
ret = i915_gem_user_to_context_sseu(&i915->gt, &user_sseu, sseu);
if (ret)
return ret;
args->size = sizeof(user_sseu);
return 0;
}
static int set_proto_ctx_param(struct drm_i915_file_private *fpriv,
struct i915_gem_proto_context *pc,
struct drm_i915_gem_context_param *args)
{
int ret = 0;
switch (args->param) {
case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
if (args->size)
ret = -EINVAL;
else if (args->value)
pc->user_flags |= BIT(UCONTEXT_NO_ERROR_CAPTURE);
else
pc->user_flags &= ~BIT(UCONTEXT_NO_ERROR_CAPTURE);
break;
case I915_CONTEXT_PARAM_BANNABLE:
if (args->size)
ret = -EINVAL;
else if (!capable(CAP_SYS_ADMIN) && !args->value)
ret = -EPERM;
else if (args->value)
pc->user_flags |= BIT(UCONTEXT_BANNABLE);
else
pc->user_flags &= ~BIT(UCONTEXT_BANNABLE);
break;
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
else if (args->value)
pc->user_flags |= BIT(UCONTEXT_RECOVERABLE);
else
pc->user_flags &= ~BIT(UCONTEXT_RECOVERABLE);
break;
case I915_CONTEXT_PARAM_PRIORITY:
ret = validate_priority(fpriv->dev_priv, args);
if (!ret)
pc->sched.priority = args->value;
break;
case I915_CONTEXT_PARAM_SSEU:
ret = set_proto_ctx_sseu(fpriv, pc, args);
break;
case I915_CONTEXT_PARAM_VM:
ret = set_proto_ctx_vm(fpriv, pc, args);
break;
case I915_CONTEXT_PARAM_ENGINES:
ret = set_proto_ctx_engines(fpriv, pc, args);
break;
case I915_CONTEXT_PARAM_PERSISTENCE:
if (args->size)
ret = -EINVAL;
ret = proto_context_set_persistence(fpriv->dev_priv, pc,
args->value);
break;
case I915_CONTEXT_PARAM_NO_ZEROMAP:
case I915_CONTEXT_PARAM_BAN_PERIOD:
case I915_CONTEXT_PARAM_RINGSIZE:
default:
ret = -EINVAL;
break;
}
return ret;
}
static struct i915_address_space *
context_get_vm_rcu(struct i915_gem_context *ctx)
{
GEM_BUG_ON(!rcu_access_pointer(ctx->vm));
do {
struct i915_address_space *vm;
/*
* We do not allow downgrading from full-ppgtt [to a shared
* global gtt], so ctx->vm cannot become NULL.
*/
vm = rcu_dereference(ctx->vm);
if (!kref_get_unless_zero(&vm->ref))
continue;
/*
* This ppgtt may have be reallocated between
* the read and the kref, and reassigned to a third
* context. In order to avoid inadvertent sharing
* of this ppgtt with that third context (and not
* src), we have to confirm that we have the same
* ppgtt after passing through the strong memory
* barrier implied by a successful
* kref_get_unless_zero().
*
* Once we have acquired the current ppgtt of ctx,
* we no longer care if it is released from ctx, as
* it cannot be reallocated elsewhere.
*/
if (vm == rcu_access_pointer(ctx->vm))
return rcu_pointer_handoff(vm);
i915_vm_put(vm);
} while (1);
}
static int intel_context_set_gem(struct intel_context *ce,
struct i915_gem_context *ctx,
struct intel_sseu sseu)
{
int ret = 0;
GEM_BUG_ON(rcu_access_pointer(ce->gem_context));
RCU_INIT_POINTER(ce->gem_context, ctx);
ce->ring_size = SZ_16K;
if (rcu_access_pointer(ctx->vm)) {
struct i915_address_space *vm;
rcu_read_lock();
vm = context_get_vm_rcu(ctx); /* hmm */
rcu_read_unlock();
i915_vm_put(ce->vm);
ce->vm = vm;
}
if (ctx->sched.priority >= I915_PRIORITY_NORMAL &&
intel_engine_has_timeslices(ce->engine))
__set_bit(CONTEXT_USE_SEMAPHORES, &ce->flags);
if (IS_ACTIVE(CONFIG_DRM_I915_REQUEST_TIMEOUT) &&
ctx->i915->params.request_timeout_ms) {
unsigned int timeout_ms = ctx->i915->params.request_timeout_ms;
intel_context_set_watchdog_us(ce, (u64)timeout_ms * 1000);
}
/* A valid SSEU has no zero fields */
if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))
ret = intel_context_reconfigure_sseu(ce, sseu);
return ret;
}
static void __free_engines(struct i915_gem_engines *e, unsigned int count)
{
while (count--) {
if (!e->engines[count])
continue;
intel_context_put(e->engines[count]);
}
kfree(e);
}
static void free_engines(struct i915_gem_engines *e)
{
__free_engines(e, e->num_engines);
}
static void free_engines_rcu(struct rcu_head *rcu)
{
struct i915_gem_engines *engines =
container_of(rcu, struct i915_gem_engines, rcu);
i915_sw_fence_fini(&engines->fence);
free_engines(engines);
}
static int __i915_sw_fence_call
engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
{
struct i915_gem_engines *engines =
container_of(fence, typeof(*engines), fence);
switch (state) {
case FENCE_COMPLETE:
if (!list_empty(&engines->link)) {
struct i915_gem_context *ctx = engines->ctx;
unsigned long flags;
spin_lock_irqsave(&ctx->stale.lock, flags);
list_del(&engines->link);
spin_unlock_irqrestore(&ctx->stale.lock, flags);
}
i915_gem_context_put(engines->ctx);
break;
case FENCE_FREE:
init_rcu_head(&engines->rcu);
call_rcu(&engines->rcu, free_engines_rcu);
break;
}
return NOTIFY_DONE;
}
static struct i915_gem_engines *alloc_engines(unsigned int count)
{
struct i915_gem_engines *e;
e = kzalloc(struct_size(e, engines, count), GFP_KERNEL);
if (!e)
return NULL;
i915_sw_fence_init(&e->fence, engines_notify);
return e;
}
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx,
struct intel_sseu rcs_sseu)
{
const struct intel_gt *gt = &ctx->i915->gt;
struct intel_engine_cs *engine;
struct i915_gem_engines *e, *err;
enum intel_engine_id id;
e = alloc_engines(I915_NUM_ENGINES);
if (!e)
return ERR_PTR(-ENOMEM);
for_each_engine(engine, gt, id) {
struct intel_context *ce;
struct intel_sseu sseu = {};
int ret;
if (engine->legacy_idx == INVALID_ENGINE)
continue;
GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES);
GEM_BUG_ON(e->engines[engine->legacy_idx]);
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
err = ERR_CAST(ce);
goto free_engines;
}
e->engines[engine->legacy_idx] = ce;
e->num_engines = max(e->num_engines, engine->legacy_idx + 1);
if (engine->class == RENDER_CLASS)
sseu = rcs_sseu;
ret = intel_context_set_gem(ce, ctx, sseu);
if (ret) {
err = ERR_PTR(ret);
goto free_engines;
}
}
return e;
free_engines:
free_engines(e);
return err;
}
static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
unsigned int num_engines,
struct i915_gem_proto_engine *pe)
{
struct i915_gem_engines *e, *err;
unsigned int n;
e = alloc_engines(num_engines);
for (n = 0; n < num_engines; n++) {
struct intel_context *ce;
int ret;
switch (pe[n].type) {
case I915_GEM_ENGINE_TYPE_PHYSICAL:
ce = intel_context_create(pe[n].engine);
break;
case I915_GEM_ENGINE_TYPE_BALANCED:
ce = intel_execlists_create_virtual(pe[n].siblings,
pe[n].num_siblings);
break;
case I915_GEM_ENGINE_TYPE_INVALID:
default:
GEM_WARN_ON(pe[n].type != I915_GEM_ENGINE_TYPE_INVALID);
continue;
}
if (IS_ERR(ce)) {
err = ERR_CAST(ce);
goto free_engines;
}
e->engines[n] = ce;
ret = intel_context_set_gem(ce, ctx, pe->sseu);
if (ret) {
err = ERR_PTR(ret);
goto free_engines;
}
}
e->num_engines = num_engines;
return e;
free_engines:
free_engines(e);
return err;
}
void i915_gem_context_release(struct kref *ref)
{
struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
trace_i915_context_free(ctx);
GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
mutex_destroy(&ctx->engines_mutex);
mutex_destroy(&ctx->lut_mutex);
put_pid(ctx->pid);
mutex_destroy(&ctx->mutex);
kfree_rcu(ctx, rcu);
}
static inline struct i915_gem_engines *