forked from torvalds/linux
/
anx7625.c
2349 lines (1933 loc) · 58.4 KB
/
anx7625.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright(c) 2020, Analogix Semiconductor. All rights reserved.
*
*/
#include <linux/gcd.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/workqueue.h>
#include <linux/of_gpio.h>
#include <linux/of_graph.h>
#include <linux/of_platform.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
#include <sound/hdmi-codec.h>
#include <video/display_timing.h>
#include "anx7625.h"
/*
* There is a sync issue while access I2C register between AP(CPU) and
* internal firmware(OCM), to avoid the race condition, AP should access
* the reserved slave address before slave address occurs changes.
*/
static int i2c_access_workaround(struct anx7625_data *ctx,
struct i2c_client *client)
{
u8 offset;
struct device *dev = &client->dev;
int ret;
if (client == ctx->last_client)
return 0;
ctx->last_client = client;
if (client == ctx->i2c.tcpc_client)
offset = RSVD_00_ADDR;
else if (client == ctx->i2c.tx_p0_client)
offset = RSVD_D1_ADDR;
else if (client == ctx->i2c.tx_p1_client)
offset = RSVD_60_ADDR;
else if (client == ctx->i2c.rx_p0_client)
offset = RSVD_39_ADDR;
else if (client == ctx->i2c.rx_p1_client)
offset = RSVD_7F_ADDR;
else
offset = RSVD_00_ADDR;
ret = i2c_smbus_write_byte_data(client, offset, 0x00);
if (ret < 0)
DRM_DEV_ERROR(dev,
"fail to access i2c id=%x\n:%x",
client->addr, offset);
return ret;
}
static int anx7625_reg_read(struct anx7625_data *ctx,
struct i2c_client *client, u8 reg_addr)
{
int ret;
struct device *dev = &client->dev;
i2c_access_workaround(ctx, client);
ret = i2c_smbus_read_byte_data(client, reg_addr);
if (ret < 0)
DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n",
client->addr, reg_addr);
return ret;
}
static int anx7625_reg_block_read(struct anx7625_data *ctx,
struct i2c_client *client,
u8 reg_addr, u8 len, u8 *buf)
{
int ret;
struct device *dev = &client->dev;
i2c_access_workaround(ctx, client);
ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf);
if (ret < 0)
DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n",
client->addr, reg_addr);
return ret;
}
static int anx7625_reg_write(struct anx7625_data *ctx,
struct i2c_client *client,
u8 reg_addr, u8 reg_val)
{
int ret;
struct device *dev = &client->dev;
i2c_access_workaround(ctx, client);
ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val);
if (ret < 0)
DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x",
client->addr, reg_addr);
return ret;
}
static int anx7625_write_or(struct anx7625_data *ctx,
struct i2c_client *client,
u8 offset, u8 mask)
{
int val;
val = anx7625_reg_read(ctx, client, offset);
if (val < 0)
return val;
return anx7625_reg_write(ctx, client, offset, (val | (mask)));
}
static int anx7625_write_and(struct anx7625_data *ctx,
struct i2c_client *client,
u8 offset, u8 mask)
{
int val;
val = anx7625_reg_read(ctx, client, offset);
if (val < 0)
return val;
return anx7625_reg_write(ctx, client, offset, (val & (mask)));
}
static int anx7625_write_and_or(struct anx7625_data *ctx,
struct i2c_client *client,
u8 offset, u8 and_mask, u8 or_mask)
{
int val;
val = anx7625_reg_read(ctx, client, offset);
if (val < 0)
return val;
return anx7625_reg_write(ctx, client,
offset, (val & and_mask) | (or_mask));
}
static int anx7625_config_bit_matrix(struct anx7625_data *ctx)
{
int i, ret;
ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
AUDIO_CONTROL_REGISTER, 0x80);
for (i = 0; i < 13; i++)
ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
VIDEO_BIT_MATRIX_12 + i,
0x18 + i);
return ret;
}
static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
{
return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
}
static int wait_aux_op_finish(struct anx7625_data *ctx)
{
struct device *dev = &ctx->client->dev;
int val;
int ret;
ret = readx_poll_timeout(anx7625_read_ctrl_status_p0,
ctx, val,
(!(val & AP_AUX_CTRL_OP_EN) || (val < 0)),
2000,
2000 * 150);
if (ret) {
DRM_DEV_ERROR(dev, "aux operation fail!\n");
return -EIO;
}
val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
AP_AUX_CTRL_STATUS);
if (val < 0 || (val & 0x0F)) {
DRM_DEV_ERROR(dev, "aux status %02x\n", val);
return -EIO;
}
return 0;
}
static int anx7625_video_mute_control(struct anx7625_data *ctx,
u8 status)
{
int ret;
if (status) {
/* Set mute on flag */
ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
AP_AV_STATUS, AP_MIPI_MUTE);
/* Clear mipi RX en */
ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
AP_AV_STATUS, (u8)~AP_MIPI_RX_EN);
} else {
/* Mute off flag */
ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
/* Set MIPI RX EN */
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
AP_AV_STATUS, AP_MIPI_RX_EN);
}
return ret;
}
/* Reduction of fraction a/b */
static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b)
{
unsigned long gcd_num;
unsigned long tmp_a, tmp_b;
u32 i = 1;
gcd_num = gcd(*a, *b);
*a /= gcd_num;
*b /= gcd_num;
tmp_a = *a;
tmp_b = *b;
while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) {
i++;
*a = tmp_a / i;
*b = tmp_b / i;
}
/*
* In the end, make a, b larger to have higher ODFC PLL
* output frequency accuracy
*/
while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) {
*a <<= 1;
*b <<= 1;
}
*a >>= 1;
*b >>= 1;
}
static int anx7625_calculate_m_n(u32 pixelclock,
unsigned long *m,
unsigned long *n,
u8 *post_divider)
{
if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) {
/* Pixel clock frequency is too high */
DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n",
pixelclock,
PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN);
return -EINVAL;
}
if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) {
/* Pixel clock frequency is too low */
DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n",
pixelclock,
PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX);
return -EINVAL;
}
for (*post_divider = 1;
pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));)
*post_divider += 1;
if (*post_divider > POST_DIVIDER_MAX) {
for (*post_divider = 1;
(pixelclock <
(PLL_OUT_FREQ_ABS_MIN / (*post_divider)));)
*post_divider += 1;
if (*post_divider > POST_DIVIDER_MAX) {
DRM_ERROR("cannot find property post_divider(%d)\n",
*post_divider);
return -EDOM;
}
}
/* Patch to improve the accuracy */
if (*post_divider == 7) {
/* 27,000,000 is not divisible by 7 */
*post_divider = 8;
} else if (*post_divider == 11) {
/* 27,000,000 is not divisible by 11 */
*post_divider = 12;
} else if ((*post_divider == 13) || (*post_divider == 14)) {
/* 27,000,000 is not divisible by 13 or 14 */
*post_divider = 15;
}
if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) {
DRM_ERROR("act clock(%u) large than maximum(%lu)\n",
pixelclock * (*post_divider),
PLL_OUT_FREQ_ABS_MAX);
return -EDOM;
}
*m = pixelclock;
*n = XTAL_FRQ / (*post_divider);
anx7625_reduction_of_a_fraction(m, n);
return 0;
}
static int anx7625_odfc_config(struct anx7625_data *ctx,
u8 post_divider)
{
int ret;
struct device *dev = &ctx->client->dev;
/* Config input reference clock frequency 27MHz/19.2MHz */
ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
~(REF_CLK_27000KHZ << MIPI_FREF_D_IND));
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
(REF_CLK_27000KHZ << MIPI_FREF_D_IND));
/* Post divider */
ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
MIPI_DIGITAL_PLL_8, 0x0f);
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8,
post_divider << 4);
/* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */
ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
~MIPI_PLL_VCO_TUNE_REG_VAL);
/* Reset ODFC PLL */
ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
~MIPI_PLL_RESET_N);
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
MIPI_PLL_RESET_N);
if (ret < 0)
DRM_DEV_ERROR(dev, "IO error.\n");
return ret;
}
static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
{
struct device *dev = &ctx->client->dev;
unsigned long m, n;
u16 htotal;
int ret;
u8 post_divider = 0;
ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000,
&m, &n, &post_divider);
if (ret) {
DRM_DEV_ERROR(dev, "cannot get property m n value.\n");
return ret;
}
DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n",
m, n, post_divider);
/* Configure pixel clock */
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L,
(ctx->dt.pixelclock.min / 1000) & 0xFF);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H,
(ctx->dt.pixelclock.min / 1000) >> 8);
/* Lane count */
ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
MIPI_LANE_CTRL_0, 0xfc);
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client,
MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1);
/* Htotal */
htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8);
/* Hactive */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8);
/* HFP */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_FRONT_PORCH_H,
ctx->dt.hfront_porch.min >> 8);
/* HWS */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8);
/* HBP */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8);
/* Vactive */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L,
ctx->dt.vactive.min);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H,
ctx->dt.vactive.min >> 8);
/* VFP */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min);
/* VWS */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min);
/* VBP */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min);
/* M value */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_PLL_M_NUM_7_0, (m & 0xff));
/* N value */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
(n & 0xff));
/* Diff */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_DIGITAL_ADJ_1, 0x3D);
ret |= anx7625_odfc_config(ctx, post_divider - 1);
if (ret < 0)
DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n");
return ret;
}
static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx)
{
int val;
struct device *dev = &ctx->client->dev;
/* Swap MIPI-DSI data lane 3 P and N */
val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP);
if (val < 0) {
DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n");
return -EIO;
}
val |= (1 << MIPI_SWAP_CH3);
return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val);
}
static int anx7625_api_dsi_config(struct anx7625_data *ctx)
{
int val, ret;
struct device *dev = &ctx->client->dev;
/* Swap MIPI-DSI data lane 3 P and N */
ret = anx7625_swap_dsi_lane3(ctx);
if (ret < 0) {
DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n");
return ret;
}
/* DSI clock settings */
val = (0 << MIPI_HS_PWD_CLK) |
(0 << MIPI_HS_RT_CLK) |
(0 << MIPI_PD_CLK) |
(1 << MIPI_CLK_RT_MANUAL_PD_EN) |
(1 << MIPI_CLK_HS_MANUAL_PD_EN) |
(0 << MIPI_CLK_DET_DET_BYPASS) |
(0 << MIPI_CLK_MISS_CTRL) |
(0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN);
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_PHY_CONTROL_3, val);
/*
* Decreased HS prepare timing delay from 160ns to 80ns work with
* a) Dragon board 810 series (Qualcomm AP)
* b) Moving Pixel DSI source (PG3A pattern generator +
* P332 D-PHY Probe) default D-PHY timing
* 5ns/step
*/
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_TIME_HS_PRPR, 0x10);
/* Enable DSI mode*/
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18,
SELECT_DSI << MIPI_DPI_SELECT);
ret |= anx7625_dsi_video_timing_config(ctx);
if (ret < 0) {
DRM_DEV_ERROR(dev, "dsi video timing config fail\n");
return ret;
}
/* Toggle m, n ready */
ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
~(MIPI_M_NUM_READY | MIPI_N_NUM_READY));
usleep_range(1000, 1100);
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
MIPI_M_NUM_READY | MIPI_N_NUM_READY);
/* Configure integer stable register */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_VIDEO_STABLE_CNT, 0x02);
/* Power on MIPI RX */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_LANE_CTRL_10, 0x00);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_LANE_CTRL_10, 0x80);
if (ret < 0)
DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n");
return ret;
}
static int anx7625_dsi_config(struct anx7625_data *ctx)
{
struct device *dev = &ctx->client->dev;
int ret;
DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n");
/* DSC disable */
ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
R_DSC_CTRL_0, ~DSC_EN);
ret |= anx7625_api_dsi_config(ctx);
if (ret < 0) {
DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n");
return ret;
}
/* Set MIPI RX EN */
ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
AP_AV_STATUS, AP_MIPI_RX_EN);
/* Clear mute flag */
ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
if (ret < 0)
DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n");
else
DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n");
return ret;
}
static int anx7625_api_dpi_config(struct anx7625_data *ctx)
{
struct device *dev = &ctx->client->dev;
u16 freq = ctx->dt.pixelclock.min / 1000;
int ret;
/* configure pixel clock */
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
PIXEL_CLOCK_L, freq & 0xFF);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
PIXEL_CLOCK_H, (freq >> 8));
/* set DPI mode */
/* set to DPI PLL module sel */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_DIGITAL_PLL_9, 0x20);
/* power down MIPI */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_LANE_CTRL_10, 0x08);
/* enable DPI mode */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
MIPI_DIGITAL_PLL_18, 0x1C);
/* set first edge */
ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
VIDEO_CONTROL_0, 0x06);
if (ret < 0)
DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n");
return ret;
}
static int anx7625_dpi_config(struct anx7625_data *ctx)
{
struct device *dev = &ctx->client->dev;
int ret;
DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n");
/* DSC disable */
ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
R_DSC_CTRL_0, ~DSC_EN);
if (ret < 0) {
DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n");
return ret;
}
ret = anx7625_config_bit_matrix(ctx);
if (ret < 0) {
DRM_DEV_ERROR(dev, "config bit matrix failed.\n");
return ret;
}
ret = anx7625_api_dpi_config(ctx);
if (ret < 0) {
DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n");
return ret;
}
/* set MIPI RX EN */
ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
AP_AV_STATUS, AP_MIPI_RX_EN);
/* clear mute flag */
ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
if (ret < 0)
DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n");
return ret;
}
static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
u8 addrh, u8 addrm, u8 addrl,
u8 len, u8 *buf)
{
struct device *dev = &ctx->client->dev;
int ret;
u8 cmd;
if (len > MAX_DPCD_BUFFER_SIZE) {
DRM_DEV_ERROR(dev, "exceed aux buffer len.\n");
return -E2BIG;
}
cmd = ((len - 1) << 4) | 0x09;
/* Set command and length */
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_COMMAND, cmd);
/* Set aux access address */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_ADDR_7_0, addrl);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_ADDR_15_8, addrm);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_ADDR_19_16, addrh);
/* Enable aux access */
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
if (ret < 0) {
DRM_DEV_ERROR(dev, "cannot access aux related register.\n");
return -EIO;
}
usleep_range(2000, 2100);
ret = wait_aux_op_finish(ctx);
if (ret) {
DRM_DEV_ERROR(dev, "aux IO error: wait aux op finish.\n");
return ret;
}
ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
AP_AUX_BUFF_START, len, buf);
if (ret < 0) {
DRM_DEV_ERROR(dev, "read dpcd register failed\n");
return -EIO;
}
return 0;
}
static int anx7625_read_flash_status(struct anx7625_data *ctx)
{
return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
}
static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
{
int ret, val;
struct device *dev = &ctx->client->dev;
u8 ident[32];
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
FLASH_ADDR_HIGH, 0x91);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
FLASH_ADDR_LOW, 0xA0);
if (ret < 0) {
DRM_DEV_ERROR(dev, "IO error : set key flash address.\n");
return ret;
}
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
if (ret < 0) {
DRM_DEV_ERROR(dev, "IO error : set key flash len.\n");
return ret;
}
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
R_FLASH_RW_CTRL, FLASH_READ);
ret |= readx_poll_timeout(anx7625_read_flash_status,
ctx, val,
((val & FLASH_DONE) || (val < 0)),
2000,
2000 * 150);
if (ret) {
DRM_DEV_ERROR(dev, "flash read access fail!\n");
return -EIO;
}
ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
FLASH_BUF_BASE_ADDR,
FLASH_BUF_LEN, ident);
if (ret < 0) {
DRM_DEV_ERROR(dev, "read flash data fail!\n");
return -EIO;
}
if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF)
return -EINVAL;
return 0;
}
static int anx7625_hdcp_setting(struct anx7625_data *ctx)
{
u8 bcap;
int ret;
struct device *dev = &ctx->client->dev;
ret = anx7625_hdcp_key_probe(ctx);
if (ret) {
DRM_DEV_DEBUG_DRIVER(dev, "disable HDCP by config\n");
return anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
0xee, 0x9f);
}
anx7625_aux_dpcd_read(ctx, 0x06, 0x80, 0x28, 1, &bcap);
if (!(bcap & 0x01)) {
DRM_DEV_DEBUG_DRIVER(dev, "bcap(0x%x) not support HDCP 1.4.\n",
bcap);
return anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
0xee, 0x9f);
}
DRM_DEV_DEBUG_DRIVER(dev, "enable HDCP 1.4\n");
ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
/* Try auth flag */
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
/* Interrupt for DRM */
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
if (ret < 0)
DRM_DEV_ERROR(dev, "fail to enable HDCP\n");
return ret;
}
static void anx7625_dp_start(struct anx7625_data *ctx)
{
int ret;
struct device *dev = &ctx->client->dev;
if (!ctx->display_timing_valid) {
DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n");
return;
}
/* HDCP config */
anx7625_hdcp_setting(ctx);
if (ctx->pdata.is_dpi)
ret = anx7625_dpi_config(ctx);
else
ret = anx7625_dsi_config(ctx);
if (ret < 0)
DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
}
static void anx7625_dp_stop(struct anx7625_data *ctx)
{
struct device *dev = &ctx->client->dev;
int ret;
DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n");
/*
* Video disable: 0x72:08 bit 7 = 0;
* Audio disable: 0x70:87 bit 0 = 0;
*/
ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe);
ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
ret |= anx7625_video_mute_control(ctx, 1);
if (ret < 0)
DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
}
static int sp_tx_rst_aux(struct anx7625_data *ctx)
{
int ret;
ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
AUX_RST);
ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
~AUX_RST);
return ret;
}
static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset)
{
int ret;
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_BUFF_START, offset);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_COMMAND, 0x04);
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
return (ret | wait_aux_op_finish(ctx));
}
static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd)
{
int ret;
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_COMMAND, len_cmd);
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
return (ret | wait_aux_op_finish(ctx));
}
static int sp_tx_get_edid_block(struct anx7625_data *ctx)
{
int c = 0;
struct device *dev = &ctx->client->dev;
sp_tx_aux_wr(ctx, 0x7e);
sp_tx_aux_rd(ctx, 0x01);
c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START);
if (c < 0) {
DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n");
return -EIO;
}
DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1);
if (c > MAX_EDID_BLOCK)
c = 1;
return c;
}
static int edid_read(struct anx7625_data *ctx,
u8 offset, u8 *pblock_buf)
{
int ret, cnt;
struct device *dev = &ctx->client->dev;
for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
sp_tx_aux_wr(ctx, offset);
/* Set I2C read com 0x01 mot = 0 and read 16 bytes */
ret = sp_tx_aux_rd(ctx, 0xf1);
if (ret) {
sp_tx_rst_aux(ctx);
DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n");
} else {
ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
AP_AUX_BUFF_START,
MAX_DPCD_BUFFER_SIZE,
pblock_buf);
if (ret > 0)
break;
}
}
if (cnt > EDID_TRY_CNT)
return -EIO;
return 0;
}
static int segments_edid_read(struct anx7625_data *ctx,
u8 segment, u8 *buf, u8 offset)
{
u8 cnt;
int ret;
struct device *dev = &ctx->client->dev;
/* Write address only */
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_ADDR_7_0, 0x30);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_COMMAND, 0x04);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_CTRL_STATUS,
AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN);
ret |= wait_aux_op_finish(ctx);
/* Write segment address */
ret |= sp_tx_aux_wr(ctx, segment);
/* Data read */
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_ADDR_7_0, 0x50);
if (ret) {
DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n");
return ret;
}
for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
sp_tx_aux_wr(ctx, offset);
/* Set I2C read com 0x01 mot = 0 and read 16 bytes */
ret = sp_tx_aux_rd(ctx, 0xf1);
if (ret) {
ret = sp_tx_rst_aux(ctx);
DRM_DEV_ERROR(dev, "segment read fail, reset!\n");
} else {
ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
AP_AUX_BUFF_START,
MAX_DPCD_BUFFER_SIZE, buf);
if (ret > 0)
break;
}
}
if (cnt > EDID_TRY_CNT)
return -EIO;
return 0;
}
static int sp_tx_edid_read(struct anx7625_data *ctx,
u8 *pedid_blocks_buf)
{
u8 offset, edid_pos;
int count, blocks_num;
u8 pblock_buf[MAX_DPCD_BUFFER_SIZE];
u8 i, j;
u8 g_edid_break = 0;
int ret;
struct device *dev = &ctx->client->dev;
/* Address initial */
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_ADDR_7_0, 0x50);
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_ADDR_15_8, 0);
ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
AP_AUX_ADDR_19_16, 0xf0);
if (ret < 0) {
DRM_DEV_ERROR(dev, "access aux channel IO error.\n");
return -EIO;
}
blocks_num = sp_tx_get_edid_block(ctx);
if (blocks_num < 0)
return blocks_num;
count = 0;