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ARM.Cortex_DFP.pdsc
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ARM.Cortex_DFP.pdsc
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<?xml version="1.0" encoding="UTF-8"?>
<package schemaVersion="1.7.33" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/v1.7.33/schema/PACK.xsd">
<name>Cortex_DFP</name>
<description>ARM Cortex Reference Subsystems Device Family Pack</description>
<vendor>ARM</vendor>
<license>LICENSE</license>
<licenseSets>
<licenseSet id="all" default="true" gating="true">
<license name="LICENSE" title="Apache 2.0 open-source license" spdx="Apache-2.0"/>
</licenseSet>
</licenseSets>
<url>https://www.keil.com/pack/</url>
<repository type="git">https:/github.com/arm-software/Cortex_DFP.git</repository>
<releases>
<release version="0.0.0">
Active development ...
</release>
</releases>
<requirements>
<packages>
<package vendor="ARM" name="CMSIS" version="6.0.0-0"/>
</packages>
</requirements>
<devices>
<!-- ****************************** Cortex-M0 ****************************** -->
<family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
<description>
The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications.
It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family
</description>
<book name="https://developer.arm.com/documentation/dui0497" title="Cortex-M0 Processor Devices Generic Users Guide"/>
<device Dname="ARMCM0">
<processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
<memory name="ROM" access="rx" start="0x00000000" size="0x00040000" default="1" startup="1"/>
<memory name="RAM" access="rwx" start="0x20000000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M0P ****************************** -->
<family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
<description>
The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications.
It offers significant benefits to developers, including:
- A simple architecture that is easy to learn and program
- Ultra-low power, energy-efficient operation
- Excellent code density
- Deterministic, high-performance interrupt handling
- Upward compatibility with Cortex-M processor family
- Platform security robustness, with optional integrated Memory Protection Unit (MPU)
</description>
<book name="https://developer.arm.com/documentation/dui0662" title="Cortex-M0+ Processor Devices Generic Users Guide"/>
<device Dname="ARMCM0P">
<processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
<memory name="ROM" access="rx" start="0x00000000" size="0x00040000" default="1" startup="1"/>
<memory name="RAM" access="rwx" start="0x20000000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M1 ****************************** -->
<family Dfamily="ARM Cortex M1" Dvendor="ARM:82">
<description>
The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA.
The ARM Cortex-M1 processor implements the ARMv6-M architecture profile.
</description>
<!--book name="https://developer.arm.com/documentation/??" title="Cortex-M1 Processor Devices Generic Users Guide"/-->
<device Dname="ARMCM1">
<processor Dcore="Cortex-M1" DcoreVersion="r1p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM1/Include/ARMCM1.h" define="ARMCM1"/>
<memory name="ROM" access="rx" start="0x00000000" size="0x00040000" default="1" startup="1"/>
<memory name="RAM" access="rwx" start="0x20000000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M3 ****************************** -->
<family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
<description>
The Cortex-M3 processor is a high performance 32-bit processor designed for the microcontroller market.
It offers significant benefits to developers, including:
- outstanding processing performance combined with fast interrupt handling
- enhanced system debug with extensive breakpoint and trace capabilities
- efficient processor core, system and memories
- ultra-low power consumption with integrated sleep mode and an optional deep sleep mode
- platform security robustness, with an optional integrated Memory Protection Unit (MPU)
</description>
<book name="https://developer.arm.com/documentation/dui0552" title="Cortex-M3 Processor Devices Generic Users Guide"/>
<device Dname="ARMCM3">
<processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
<memory name="ROM" access="rx" start="0x00000000" size="0x00040000" default="1" startup="1"/>
<memory name="RAM" access="rwx" start="0x20000000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M4 ****************************** -->
<family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
<description>
The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market.
It offers significant benefits to developers, including:
- outstanding processing performance combined with fast interrupt handling
- enhanced system debug with extensive breakpoint and trace capabilities
- efficient processor core, system and memories
- ultra-low power consumption with integrated sleep mode and an optional deep sleep mode
- platform security robustness, with optional integrated Memory Protection Unit (MPU)
</description>
<book name="https://developer.arm.com/documentation/dui0553" title="Cortex-M4 Processor Devices Generic Users Guide"/>
<device Dname="ARMCM4">
<processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM4/Include/ARMCM4.h" define="ARMCM4"/>
<memory name="ROM" access="rx" start="0x00000000" size="0x00040000" default="1" startup="1"/>
<memory name="RAM" access="rwx" start="0x20000000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M7 ****************************** -->
<family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
<description>
The Cortex-M7 processor is a high performance 32-bit processor designed for the microcontroller market.
It offers significant benefits to developers, including:
- Outstanding processing performance combined with fast interrupt handling
- Enhanced system debug with extensive breakpoint and trace capabilities
- Efficient processor core, system and memories
- Ultra-low power consumption with integrated sleep mode and an optional deep sleep mode
- Platform security robustness, with optional integrated Memory Protection Unit (MPU)
</description>
<book name="https://developer.arm.com/documentation/dui0646" title="Cortex-M7 Processor Devices Generic Users Guide"/>
<device Dname="ARMCM7">
<processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
<memory name="ROM" access="rx" start="0x00000000" size="0x00040000" default="1" startup="1"/>
<memory name="RAM" access="rwx" start="0x20000000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M23 ********************** -->
<family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
<description>
The Cortex-M23 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications.
It offers significant benefits to developers, including:
- A simple architecture that is easy to learn and program
- Ultra-low power, energy-efficient operation
- Excellent code density
- Deterministic, high-performance interrupt handling
- Upward compatibility with Cortex-M processor family
- Platform security robustness, with optional integrated memory protection
- Extended security features, with optional Security Extension for Armv8-M
</description>
<book name="https://developer.arm.com/documentation/dui1095" title="Cortex-M23 Processor Devices Generic Users Guide"/>
<device Dname="ARMCM23">
<processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
<memory name="ROM_S" access="rxs" start="0x00000000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_S" access="rwxs" start="0x20000000" size="0x00020000" default="1"/>
<memory name="ROM_NS" access="rxn" start="0x00200000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_NS" access="rwxn" start="0x20200000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M33 ****************************** -->
<family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
<description>
The Cortex®-M33 processor is a high-performance 32-bit processor that is designed for the microcontroller market.
The processor offers outstanding performance, fast interrupt handling, and enhanced system debug with extensive breakpoint and trace capabilities.
Other significant benefits to developers include:
- Efficient processor core, system, and memories
- Instruction set extension for signal processing applications
- Ultra-low power consumption with integrated sleep modes
- Platform robustness with optional integrated memory protection
- Extended security features with optional Security Extension for Armv8-M
</description>
<book name="https://developer.arm.com/documentation/100235" title="Cortex-M33 Processor Devices Generic Users Guide"/>
<device Dname="ARMCM33">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
<memory name="ROM_S" access="rxs" start="0x00000000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_S" access="rwxs" start="0x20000000" size="0x00020000" default="1"/>
<memory name="ROM_NS" access="rxn" start="0x00200000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_NS" access="rwxn" start="0x20200000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M35P ****************************** -->
<family Dfamily="ARM Cortex M35P" Dvendor="ARM:82">
<description>
The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller
class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications.
</description>
<!--book name="https://developer.arm.com/documentation/??" title="Cortex M35P Processor Devices Generic Users Guide"/-->
<device Dname="ARMCM35P">
<processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM35P/Include/ARMCM35P.h" define="ARMCM35P"/>
<memory name="ROM_S" access="rxs" start="0x00000000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_S" access="rwxs" start="0x20000000" size="0x00020000" default="1"/>
<memory name="ROM_NS" access="rxn" start="0x00200000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_NS" access="rwxn" start="0x20200000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M55 ****************************** -->
<family Dfamily="ARM Cortex M52" Dvendor="ARM:82">
<description>
The Cortex-M52 processor is a fully synthesizable mid-range microcontroller class processor that implements the Arm®v8.1-M Mainline architecture which includes support for the M-profile Vector Extension (MVE) and Pointer Authentication and Branch Target Identification (PACBTI) Extension.
The processor also supports previous Arm®v8-M architectural features.
The design is focused on compute applications such as Digital Signal Processing (DSP) and machine learning.
The Cortex-M52 processor is energy efficient and achieves high compute performance across scalar and vector operations while maintaining low power consumption.
The processor can be configured to include Dual Core Lockstep (DCLS) functionality, which implements a redundant copy of most of the processor logic.
To support Arm Custom Instructions (ACIs), the processor includes optional Custom Datapath Extension (CDE) modules, which are embedded inside the logic.
These modules are used to execute user-defined instructions that work on general-purpose integer, floating point, and MVE registers.
</description>
<book name="https://developer.arm.com/documentation/102776" title="Arm Cortex-M52 Processor Technical Reference Manual"/>
<device Dname="ARMCM52">
<processor Dcore="Cortex-M52" DcoreVersion="r0p2" Dmpu="MPU" Dfpu="DP_FPU" Dmve="FP_MVE" Dpacbti="PACBTI" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM52/Include/ARMCM52.h" define="ARMCM52"/>
<memory name="ROM_S" access="rxs" start="0x00000000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_S" access="rwxs" start="0x20000000" size="0x00020000" default="1"/>
<memory name="ROM_NS" access="rxn" start="0x00200000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_NS" access="rwxn" start="0x20200000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M55 ****************************** -->
<family Dfamily="ARM Cortex M55" Dvendor="ARM:82">
<description>
The Cortex-M55 processor is a fully synthesizeable mid-range processor that is designed for the microcontroller market.
The processor offers high compute performance across both scalar and vector operations with low power consumption, fast interrupt handling, and optional enhanced system debug with extensive breakpoint and trace capabilities.
Other significant benefits to developers include:
- Efficient processor core, system, and memories
- Instruction set extension for Digital Signal Processing (DSP) and Machine Learning applications
- Ultra-low power consumption with integrated sleep modes
- Platform robustness with optional integrated memory protection
- Extended security features with optional Security Extension
- Extended vector processing functionality with optional Armv8.1-M M-profile Vector Extension (MVE). Armv8.1-M MVE is also referred to as Arm Helium technology.
- Support for Custom Datapath Extension (CDE), which adds classes of Arm Custom Instructions (ACIs) in the coprocessor instruction space.
</description>
<book name="https://developer.arm.com/documentation/101273" title="Cortex-M55 Processor Devices Generic Users Guide"/>
<device Dname="ARMCM55">
<processor Dcore="Cortex-M55" DcoreVersion="r1p1" Dmpu="MPU" Dfpu="DP_FPU" Dmve="FP_MVE" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM55/Include/ARMCM55.h" define="ARMCM55"/>
<memory name="ROM_S" access="rxs" start="0x00000000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_S" access="rwxs" start="0x20000000" size="0x00020000" default="1"/>
<memory name="ROM_NS" access="rxn" start="0x00200000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_NS" access="rwxn" start="0x20200000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-M85 ****************************** -->
<family Dfamily="ARM Cortex M85" Dvendor="ARM:82">
<description>
The Cortex-M85 processor is a fully synthesizeable high-performance processor that is designed for the microcontroller market.
The processor offers high compute performance across both scalar and vector operations with low power consumption, fast interrupt handling, and optional enhanced system debug with extensive breakpoint and trace capabilities.
Other significant benefits to developers include:
- Efficient processor core, system, and memories.
- Instruction set extension for Digital Signal Processing (DSP) and Machine Learning applications.
- Ultra-low power consumption with integrated sleep modes.
- Platform robustness with optional integrated memory protection.
- Extended security features through the included Security Extension.
- Extended vector processing functionality with optional Armv8.1-M M-profile Vector Extension (MVE). Armv8.1-M MVE is also referred to as Arm Helium technology .
</description>
<book name="https://developer.arm.com/documentation/1019283" title="Cortex-M85 Processor Devices Generic Users Guide"/>
<device Dname="ARMCM85">
<processor Dcore="Cortex-M85" DcoreVersion="r1p0" Dmpu="MPU" Dfpu="DP_FPU" Dmve="FP_MVE" Dpacbti="PACBTI" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMCM85/Include/ARMCM85.h" define="ARMCM85"/>
<memory name="ROM_S" access="rxs" start="0x00000000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_S" access="rwxs" start="0x20000000" size="0x00020000" default="1"/>
<memory name="ROM_NS" access="rxn" start="0x00200000" size="0x00200000" default="1" startup="1"/>
<memory name="RAM_NS" access="rwxn" start="0x20200000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** ARMSC000 ****************************** -->
<family Dfamily="ARM SC000" Dvendor="ARM:82">
<description>
The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications.
It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
</description>
<device Dname="ARMSC000">
<processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
<memory name="ROM" access="rx" start="0x00000000" size="0x00040000" default="1" startup="1"/>
<memory name="RAM" access="rwx" start="0x20000000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** ARMSC300 ****************************** -->
<family Dfamily="ARM SC300" Dvendor="ARM:82">
<description>
The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications.
It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
</description>
<device Dname="ARMSC300">
<processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
<memory name="ROM" access="rx" start="0x00000000" size="0x00040000" default="1" startup="1"/>
<memory name="RAM" access="rwx" start="0x20000000" size="0x00020000" default="1"/>
</device>
</family>
<!-- ****************************** Cortex-A5 ****************************** -->
<family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
<description>
The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit Arm instructions and 16-bit and 32-bit Thumb instructions.
The Cortex-A5 is the smallest member of the Cortex-A processor family.
</description>
<book name="https://developer.arm.com/documentation/ddi0433" title="Cortex-A5 Technical Reference Manual"/>
<device Dname="ARMCA5">
<processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
<memory name="ROM1" access="rx" start="0x00000000" size="0x04000000" default="1" startup="1"/> <!-- 64MB NOR -->
<memory name="ROM2" access="rx" start="0x0C000000" size="0x04000000" default="0" startup="0"/> <!-- 64MB NOR -->
<memory name="RAM1" access="rwx" start="0x14000000" size="0x02000000" default="1"/> <!-- 32MB SRAM -->
<memory name="RAM2" access="rwx" start="0x80000000" size="0x40000000" default="0"/> <!-- 1GB DRAM -->
</device>
</family>
<!-- ****************************** Cortex-A7 ****************************** -->
<family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
<description>
The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem, an optional integrated GIC, and an optional L2 cache controller.
</description>
<book name="https://developer.arm.com/documentation/ddi0464" title="Cortex-A7 MPCore Technical Reference Manual"/>
<device Dname="ARMCA7">
<processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
<memory name="ROM1" access="rx" start="0x00000000" size="0x04000000" default="1" startup="1"/> <!-- 64MB NOR -->
<memory name="ROM2" access="rx" start="0x0C000000" size="0x04000000" default="0" startup="0"/> <!-- 64MB NOR -->
<memory name="RAM1" access="rwx" start="0x14000000" size="0x02000000" default="1"/> <!-- 32MB SRAM -->
<memory name="RAM2" access="rwx" start="0x80000000" size="0x40000000" default="0"/> <!-- 1GB DRAM -->
</device>
</family>
<!-- ****************************** Cortex-A9 ****************************** -->
<family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
<description>
The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java bytecodes in Jazelle state.
</description>
<book name="https://developer.arm.com/documentation/100511" title="Cortex-A9 Technical Reference Manual"/>
<device Dname="ARMCA9">
<processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
<memory name="ROM1" access="rx" start="0x00000000" size="0x04000000" default="1" startup="1"/> <!-- 64MB NOR -->
<memory name="ROM2" access="rx" start="0x0C000000" size="0x04000000" default="0" startup="0"/> <!-- 64MB NOR -->
<memory name="RAM1" access="rwx" start="0x14000000" size="0x02000000" default="1"/> <!-- 32MB SRAM -->
<memory name="RAM2" access="rwx" start="0x80000000" size="0x40000000" default="0"/> <!-- 1GB DRAM -->
</device>
</family>
<!-- ****************************** Cortex-A53 ****************************** -->
<family Dfamily="ARM Cortex A53" Dvendor="ARM:82">
<description>
The Cortex-A53 processor is a high efficiency processor that implements the Armv8-A architecture.
The Cortex-A53 processor has one to four cores, each with an L1 memory system and a single shared L2 cache. It can be combined with other Cortex-A CPUs in a big.LITTLE configuration.
</description>
<book name="https://developer.arm.com/documentation/ddi0500" title="Cortex-A53 Technical Reference Manual"/>
<device Dname="ARMCA53">
<processor Dcore="Cortex-A53" DcoreVersion="r0p4" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARMCA53/Include/ARMCA53.h" define="ARMCA53"/>
<memory name="ROM1" access="rx" start="0x00000000" size="0x04000000" default="1" startup="1"/> <!-- 64MB NOR -->
<memory name="ROM2" access="rx" start="0x0C000000" size="0x04000000" default="0" startup="0"/> <!-- 64MB NOR -->
<memory name="RAM1" access="rwx" start="0x14000000" size="0x02000000" default="1"/> <!-- 32MB SRAM -->
<memory name="RAM2" access="rwx" start="0x80000000" size="0x40000000" default="0"/> <!-- 1GB DRAM -->
</device>
</family>
<!-- ****************************** Cortex-R4 ****************************** -->
<family Dfamily="ARM Cortex R4" Dvendor="ARM:82">
<description>
The Arm Cortex-R4 processor is the smallest deeply embedded real-time processor based on the Armv7-R architecture.
The Cortex-R4 processor delivers high-performance, real-time responsiveness, reliability, and dependability. It offers excellent energy efficiency and cost effectiveness for ASIC, ASSP, and MCU embedded applications.
</description>
<book name="https://developer.arm.com/documentation/ddi0363" title="Cortex-R4 Technical Reference Manual"/>
<device Dname="ARMCR4">
<processor Dcore="Cortex-R4" DcoreVersion="r1p4" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARMCR4/Include/ARMCR4.h" define="ARMCR4"/>
<memory name="ROM1" access="rx" start="0x00000000" size="0x04000000" default="1" startup="1"/> <!-- 64MB NOR -->
<memory name="ROM2" access="rx" start="0x0C000000" size="0x04000000" default="0" startup="0"/> <!-- 64MB NOR -->
<memory name="RAM1" access="rwx" start="0x14000000" size="0x02000000" default="1"/> <!-- 32MB SRAM -->
<memory name="RAM2" access="rwx" start="0x80000000" size="0x40000000" default="0"/> <!-- 1GB DRAM -->
</device>
</family>
<!-- ****************************** Cortex-R5 ****************************** -->
<family Dfamily="ARM Cortex R5" Dvendor="ARM:82">
<description>
The Arm Cortex-R5 processor provides extended fault containment for real-time applications.
The Cortex-R5 processor builds on the feature set of the Cortex-R4 with enhanced error management, extended functional safety, and SoC integration features for use in deeply embedded real-time and safety-critical systems.
</description>
<book name="https://developer.arm.com/documentation/ddi0460" title="Cortex-R5 Technical Reference Manual"/>
<device Dname="ARMCR5">
<processor Dcore="Cortex-R5" DcoreVersion="r1p2" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARMCR5/Include/ARMCR5.h" define="ARMCR5"/>
<memory name="ROM1" access="rx" start="0x00000000" size="0x04000000" default="1" startup="1"/> <!-- 64MB NOR -->
<memory name="ROM2" access="rx" start="0x0C000000" size="0x04000000" default="0" startup="0"/> <!-- 64MB NOR -->
<memory name="RAM1" access="rwx" start="0x14000000" size="0x02000000" default="1"/> <!-- 32MB SRAM -->
<memory name="RAM2" access="rwx" start="0x80000000" size="0x40000000" default="0"/> <!-- 1GB DRAM -->
</device>
</family>
<!-- ****************************** Cortex-R7 ****************************** -->
<family Dfamily="ARM Cortex R7" Dvendor="ARM:82">
<description>
The Cortex-R7 processor features an 11-stage, superscalar, out-of-order pipeline with dynamic and static branch prediction, dynamic register re-naming and non-blocking Load-Store Unit. There is also an integrated Generic Interrupt Controller (GIC), Snoop Control Unit (SCU) and timers to further reduce latency and enable symmetric multiprocessing in a dual core configuration.
</description>
<book name="https://developer.arm.com/documentation/ddi0458" title="Cortex-R7 Technical Reference Manual"/>
<device Dname="ARMCR7">
<processor Dcore="Cortex-R7" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARMCR7/Include/ARMCR7.h" define="ARMCR7"/>
<memory name="ROM1" access="rx" start="0x00000000" size="0x04000000" default="1" startup="1"/> <!-- 64MB NOR -->
<memory name="ROM2" access="rx" start="0x0C000000" size="0x04000000" default="0" startup="0"/> <!-- 64MB NOR -->
<memory name="RAM1" access="rwx" start="0x14000000" size="0x02000000" default="1"/> <!-- 32MB SRAM -->
<memory name="RAM2" access="rwx" start="0x80000000" size="0x40000000" default="0"/> <!-- 1GB DRAM -->
</device>
</family>
<!-- ****************************** Cortex-R8 ****************************** -->
<family Dfamily="ARM Cortex R8" Dvendor="ARM:82">
<description>
The Cortex-R8 processor has the highest performance in its class of real-time processors.
It is a 32-bit core based on the Armv7-R architecture, with an 11-stage pipeline and superscalar out-of-order execution. The Cortex-R8 can be scaled up from single to quad-core configurations to exploit workload parallelism. Individual cores can be powered down according to workload.
</description>
<book name="https://developer.arm.com/documentation/100400" title="Cortex-R8 Technical Reference Manual"/>
<device Dname="ARMCR8">
<processor Dcore="Cortex-R8" DcoreVersion="r0p3" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARMCR8/Include/ARMCR8.h" define="ARMCR8"/>
<memory name="ROM1" access="rx" start="0x00000000" size="0x04000000" default="1" startup="1"/> <!-- 64MB NOR -->
<memory name="ROM2" access="rx" start="0x0C000000" size="0x04000000" default="0" startup="0"/> <!-- 64MB NOR -->
<memory name="RAM1" access="rwx" start="0x14000000" size="0x02000000" default="1"/> <!-- 32MB SRAM -->
<memory name="RAM2" access="rwx" start="0x80000000" size="0x40000000" default="0"/> <!-- 1GB DRAM -->
</device>
</family>
</devices>
<conditions>
<!-- TrustZone -->
<condition id="TZ Secure">
<description>TrustZone (Secure)</description>
<require Dtz="TZ"/>
<require Dsecure="Secure"/>
</condition>
<!-- compiler -->
<condition id="ARMCC6">
<accept Tcompiler="ARMCC" Toptions="AC6"/>
<accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
</condition>
<condition id="GCC">
<require Tcompiler="GCC"/>
</condition>
<condition id="IAR">
<require Tcompiler="IAR"/>
</condition>
<!-- CMSIS-Core -->
<condition id="ARMCM0 CMSIS">
<description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM0"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM0+ CMSIS">
<description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM0P*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM1 CMSIS">
<description>Generic Arm Cortex-M1 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM1"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM3 CMSIS">
<description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM3"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM4 CMSIS">
<description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM4*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM7 CMSIS">
<description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM7*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM23 CMSIS">
<description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM23*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM33 CMSIS">
<description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM33*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM35P CMSIS">
<description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM35P*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM52 CMSIS">
<description>Generic Arm Cortex-M52 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM52*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM55 CMSIS">
<description>Generic Arm Cortex-M55 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM55*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM85 CMSIS">
<description>Generic Arm Cortex-M85 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM85*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMSC000 CMSIS">
<description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMSC000"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMSC300 CMSIS">
<description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMSC300"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCA5 CMSIS">
<description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA5"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCA7 CMSIS">
<description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA7"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCA9 CMSIS">
<description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA9"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCA53 CMSIS">
<description>Generic Arm Cortex-A53 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA53"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCR4 CMSIS">
<description>Generic Arm Cortex-R4 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCR4"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCR5 CMSIS">
<description>Generic Arm Cortex-R5 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCR5"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCR7 CMSIS">
<description>Generic Arm Cortex-R7 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCR7"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCR8 CMSIS">
<description>Generic Arm Cortex-R8 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCR8"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
</conditions>
<components>
<!-- CMSIS-Startup components -->
<!-- Cortex-M0 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM0 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M0 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM0/Include/ARMCM0.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM0/Source/startup_ARMCM0.c" version="2.0.3" attr="config"/>
<file category="sourceC" name="Device/ARMCM0/Source/system_ARMCM0.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM0/Config/ARMCM0_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM0/Config/ARMCM0_gcc.ld" version="2.2.0" attr="config" condition="GCC"/>
</files>
</component>
<!-- Cortex-M0+ -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM0+ CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M0+ device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM0plus/Include/ARMCM0plus.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM0plus/Source/startup_ARMCM0plus.c" version="3.0.0" attr="config"/>
<file category="sourceC" name="Device/ARMCM0plus/Source/system_ARMCM0plus.c" version="2.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM0plus/Config/ARMCM0plus_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM0plus/Config/ARMCM0plus_gcc.ld" version="2.2.0" attr="config" condition="GCC"/>
</files>
</component>
<!-- Cortex-M1 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM1 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M1 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM1/Include/ARMCM1.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM1/Source/startup_ARMCM1.c" version="2.0.3" attr="config"/>
<file category="sourceC" name="Device/ARMCM1/Source/system_ARMCM1.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM1/Config/ARMCM1_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM1/Config/ARMCM1_gcc.ld" version="2.2.0" attr="config" condition="GCC"/>
</files>
</component>
<!-- Cortex-M3 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM3 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M3 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM3/Include/ARMCM3.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM3/Source/startup_ARMCM3.c" version="2.0.3" attr="config"/>
<file category="sourceC" name="Device/ARMCM3/Source/system_ARMCM3.c" version="1.0.1" attr="config"/>
<file category="linkerScript" name="Device/ARMCM3/Config/ARMCM3_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM3/Config/ARMCM3_gcc.ld" version="2.2.0" attr="config" condition="GCC"/>
</files>
</component>
<!-- Cortex-M4 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM4 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M4 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM4/Include/ARMCM4.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM4/Source/startup_ARMCM4.c" version="3.0.0" attr="config"/>
<file category="sourceC" name="Device/ARMCM4/Source/system_ARMCM4.c" version="2.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM4/Config/ARMCM4_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM4/Config/ARMCM4_gcc.ld" version="2.2.0" attr="config" condition="GCC"/>
</files>
</component>
<!-- Cortex-M7 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM7 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M7 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM7/Include/ARMCM7.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM7/Source/startup_ARMCM7.c" version="3.0.0" attr="config"/>
<file category="sourceC" name="Device/ARMCM7/Source/system_ARMCM7.c" version="2.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM7/Config/ARMCM7_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM7/Config/ARMCM7_gcc.ld" version="2.2.0" attr="config" condition="GCC"/>
</files>
</component>
<!-- Cortex-M23 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM23 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M23 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM23/Include/ARMCM23.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM23/Source/startup_ARMCM23.c" version="3.0.0" attr="config"/>
<file category="sourceC" name="Device/ARMCM23/Source/system_ARMCM23.c" version="2.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM23/Config/ARMCM23_ac6.sct" version="1.1.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM23/Config/ARMCM23_gcc.ld" version="2.3.0" attr="config" condition="GCC"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARMCM23/Config/partition_ARMCM23.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-M33 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM33 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M33 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM33/Include/ARMCM33.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM33/Source/startup_ARMCM33.c" version="3.0.0" attr="config"/>
<file category="sourceC" name="Device/ARMCM33/Source/system_ARMCM33.c" version="2.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM33/Config/ARMCM33_ac6.sct" version="1.1.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM33/Config/ARMCM33_gcc.ld" version="2.3.0" attr="config" condition="GCC"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARMCM33/Config/partition_ARMCM33.h" version="1.1.1" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-M35P -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM35P CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M35P device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM35P/Include/ARMCM35P.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM35P/Source/startup_ARMCM35P.c" version="3.0.0" attr="config"/>
<file category="sourceC" name="Device/ARMCM35P/Source/system_ARMCM35P.c" version="2.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM35P/Config/ARMCM35P_ac6.sct" version="1.1.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM35P/Config/ARMCM35P_gcc.ld" version="2.3.0" attr="config" condition="GCC"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARMCM35P/Config/partition_ARMCM35P.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-M52 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM52 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Cortex-M52 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM52/Include/ARMCM52.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM52/Source/startup_ARMCM52.c" version="1.0.0" attr="config"/>
<file category="sourceC" name="Device/ARMCM52/Source/system_ARMCM52.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM52/Config/ARMCM52_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM52/Config/ARMCM52_gcc.ld" version="1.0.0" attr="config" condition="GCC"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARMCM52/Config/partition_ARMCM52.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-M55 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM55 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Cortex-M55 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM55/Include/ARMCM55.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM55/Source/startup_ARMCM55.c" version="1.1.0" attr="config"/>
<file category="sourceC" name="Device/ARMCM55/Source/system_ARMCM55.c" version="1.1.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM55/Config/ARMCM55_ac6.sct" version="1.1.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM55/Config/ARMCM55_gcc.ld" version="2.3.0" attr="config" condition="GCC"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARMCM55/Config/partition_ARMCM55.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-M85 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMCM85 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Cortex-M85 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCM85/Include/ARMCM85.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMCM85/Source/startup_ARMCM85.c" version="1.0.0" attr="config"/>
<file category="sourceC" name="Device/ARMCM85/Source/system_ARMCM85.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCM85/Config/ARMCM85_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCM85/Config/ARMCM85_gcc.ld" version="2.3.0" attr="config" condition="GCC"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARMCM85/Config/partition_ARMCM85.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-SC000 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMSC000 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm SC000 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMSC000/Include/ARMSC000.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMSC000/Source/startup_ARMSC000.c" version="2.0.3" attr="config"/>
<file category="sourceC" name="Device/ARMSC000/Source/system_ARMSC000.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMSC000/Config/ARMSC000_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMSC000/Config/ARMSC000_gcc.ld" version="2.2.0" attr="config" condition="GCC"/>
</files>
</component>
<!-- Cortex-SC300 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMSC300 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm SC300 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMSC300/Include/ARMSC300.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARMSC300/Source/startup_ARMSC300.c" version="2.0.3" attr="config"/>
<file category="sourceC" name="Device/ARMSC300/Source/system_ARMSC300.c" version="1.0.1" attr="config"/>
<file category="linkerScript" name="Device/ARMSC300/Config/ARMSC300_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMSC300/Config/ARMSC300_gcc.ld" version="2.2.0" attr="config" condition="GCC"/>
</files>
</component>
<!-- Cortex-A5 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.2.0" condition="ARMCA5 CMSIS">
<description>System and Startup for Generic Arm Cortex-A5 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCA5/Include/ARMCA5.h"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARMCA5/Source/startup_ARMCA5.c" version="1.0.1" attr="config"/>
<file category="linkerScript" name="Device/ARMCA5/Config/ARMCA5_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCA5/Config/ARMCA5_gcc.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARMCA5/Config/ARMCA5_iar.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARMCA5/Source/system_ARMCA5.c" version="1.0.1" attr="config"/>
<file category="sourceC" name="Device/ARMCA5/Source/mmu_ARMCA5.c" version="1.2.0" attr="config"/>
<file category="header" name="Device/ARMCA5/Config/mem_ARMCA5.h" version="1.1.0" attr="config"/>
</files>
</component>
<!-- Cortex-A7 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.2.0" condition="ARMCA7 CMSIS">
<description>System and Startup for Generic Arm Cortex-A7 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCA7/Include/ARMCA7.h"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARMCA7/Source/startup_ARMCA7.c" version="1.0.1" attr="config"/>
<file category="linkerScript" name="Device/ARMCA7/Config/ARMCA7_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCA7/Config/ARMCA7_gcc.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARMCA7/Config/ARMCA7_iar.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARMCA7/Source/system_ARMCA7.c" version="1.0.1" attr="config"/>
<file category="sourceC" name="Device/ARMCA7/Source/mmu_ARMCA7.c" version="1.2.0" attr="config"/>
<file category="header" name="Device/ARMCA7/Config/mem_ARMCA7.h" version="1.1.0" attr="config"/>
</files>
</component>
<!-- Cortex-A9 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.2.0" condition="ARMCA9 CMSIS">
<description>System and Startup for Generic Arm Cortex-A9 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCA9/Include/ARMCA9.h"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARMCA9/Source/startup_ARMCA9.c" version="1.0.1" attr="config"/>
<file category="linkerScript" name="Device/ARMCA9/Config/ARMCA9_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCA9/Config/ARMCA9_gcc.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARMCA9/Config/ARMCA9_iar.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARMCA9/Source/system_ARMCA9.c" version="1.0.1" attr="config"/>
<file category="sourceC" name="Device/ARMCA9/Source/mmu_ARMCA9.c" version="1.2.0" attr="config"/>
<file category="header" name="Device/ARMCA9/Config/mem_ARMCA9.h" version="1.1.0" attr="config"/>
</files>
</component>
<!-- Cortex-A53 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCA53 CMSIS">
<description>System and Startup for Generic Arm Cortex-A53 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCA53/Include/ARMCA53.h"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARMCA53/Source/startup_ARMCA53.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCA53/Config/ARMCA53_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCA53/Config/ARMCA53_gcc.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARMCA53/Config/ARMCA53_iar.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARMCA53/Source/system_ARMCA53.c" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARMCA53/Config/mem_ARMCA53.h" version="1.0.0" attr="config"/>
</files>
</component>
<!-- Cortex-R4 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCR4 CMSIS">
<description>System and Startup for Generic Arm Cortex-R4 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCR4/Include/ARMCR4.h"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARMCR4/Source/startup_ARMCR4.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCR4/Config/ARMCR4_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCR4/Config/ARMCR4_gcc.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARMCR4/Config/ARMCR4_iar.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARMCR4/Source/system_ARMCR4.c" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARMCR4/Config/mem_ARMCR4.h" version="1.0.0" attr="config"/>
</files>
</component>
<!-- Cortex-R5 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCR5 CMSIS">
<description>System and Startup for Generic Arm Cortex-R5 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCR5/Include/ARMCR5.h"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARMCR5/Source/startup_ARMCR5.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCR5/Config/ARMCR5_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCR5/Config/ARMCR5_gcc.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARMCR5/Config/ARMCR5_iar.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARMCR5/Source/system_ARMCR5.c" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARMCR5/Config/mem_ARMCR5.h" version="1.0.0" attr="config"/>
</files>
</component>
<!-- Cortex-R7 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCR7 CMSIS">
<description>System and Startup for Generic Arm Cortex-R7 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARMCR7/Include/ARMCR7.h"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARMCR7/Source/startup_ARMCR7.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARMCR7/Config/ARMCR7_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARMCR7/Config/ARMCR7_gcc.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARMCR7/Config/ARMCR7_iar.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARMCR7/Source/system_ARMCR7.c" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARMCR7/Config/mem_ARMCR7.h" version="1.0.0" attr="config"/>
</files>
</component>
<!-- Cortex-R8 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCR8 CMSIS">
<description>System and Startup for Generic Arm Cortex-R8 device</description>
<files>