rainier.json

{
    "_type": "Events",
    "timestamp": "Thu Feb  8 21:07:05 2024",
    "implementer": "?",
    "cpuid": "0x3f412",
    "cpu": "Rainier",
    "architecture": "armv8.2-a",
    "pmu_architecture": "pmuv3",
    "refs": [
        {
            "ref": "Neoverse N1 TRM",
            "public": true
        },
        {
            "ref": "DDI0600 Morello Architecture Supplement",
            "public": true
        }
    ],
    "events": [
        {
            "code": 0,
            "refs": [
                0
            ],
            "name": "SW_INCR",
            "architectural": true,
            "type": "INS",
            "event_bits": 1,
            "event_lsb": 0,
            "trace_lsb": 0,
            "description": "Software increment. Instruction architecturally executed (condition code check pass)"
        },
        {
            "code": 1,
            "refs": [
                0
            ],
            "name": "L1I_CACHE_REFILL",
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1I",
            "event_bits": 1,
            "event_lsb": 1,
            "trace_lsb": 1,
            "description": "L1 instruction cache refill. This event counts any instruction fetch which misses in the cache. The following instructions are not counted: +//0 Cache maintenance instructions. +//0 Non-cacheable accesses"
        },
        {
            "code": 2,
            "refs": [
                0
            ],
            "name": "L1I_TLB_REFILL",
            "architectural": false,
            "type": "UEVT",
            "component": "L1ITLB",
            "event_bits": 1,
            "event_lsb": 2,
            "trace_lsb": 2,
            "description": "L1 instruction TLB refill. This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes refills that result in a translation fault. The following instructions are not counted: +//0 TLB maintenance instructions. This event counts regardless of whether the MMU is enabled"
        },
        {
            "code": 3,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_REFILL",
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "event_bits": 1,
            "event_lsb": 167,
            "trace_lsb": 167,
            "description": "L1 data cache refill. This event counts any load or store operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1. The following instructions are not counted: +//0 Cache maintenance instructions and prefetches. +//0 Stores of an entire cache line, even if they make a coherency request outside the L1. +//0 Partial cache line writes which do not allocate into the L1 cache. +//0 Non-cacheable accesses. This event counts the sum of L1D_CACHE_REFILL_RD and L1D_CACHE_REFILL_WR"
        },
        {
            "code": 4,
            "refs": [
                0
            ],
            "name": "L1D_CACHE",
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1D",
            "event_bits": 3,
            "event_lsb": 3,
            "trace_lsb": 3,
            "description": "L1 data cache access. This event counts any load or store operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to count. The following instructions are not counted: +//0 Cache maintenance instructions and prefetches. +//0 Non-cacheable accesses. This event counts the sum of L1D_CACHE_RD and L1D_CACHE_WR"
        },
        {
            "code": 5,
            "refs": [
                0
            ],
            "name": "L1D_TLB_REFILL",
            "architectural": false,
            "type": "UEVT",
            "component": "L1DTLB",
            "event_bits": 2,
            "event_lsb": 6,
            "trace_lsb": 6,
            "description": "L1 data TLB refill. This event counts any refill of the data L1 TLB from the L2 TLB. This includes refills that result in a translation fault. The following instructions are not counted: +//0 TLB maintenance instructions. This event counts regardless of whether the MMU is enabled"
        },
        {
            "code": 8,
            "refs": [
                0
            ],
            "name": "INST_RETIRED",
            "architectural": true,
            "type": "INS",
            "event_bits": 4,
            "event_lsb": 8,
            "trace_lsb": 8,
            "description": "Instruction architecturally executed. This event counts all retired instructions, including those that fail their condition check"
        },
        {
            "code": 9,
            "refs": [
                0
            ],
            "name": "EXC_TAKEN",
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 12,
            "trace_lsb": 12,
            "description": "Exception taken"
        },
        {
            "code": 10,
            "refs": [
                0
            ],
            "name": "EXC_RETURN",
            "architectural": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 13,
            "trace_lsb": 13,
            "description": "Instruction architecturally executed, condition code check pass, exception return"
        },
        {
            "code": 11,
            "refs": [
                0
            ],
            "name": "CID_WRITE_RETIRED",
            "architectural": true,
            "type": "INS",
            "event_bits": 1,
            "event_lsb": 156,
            "trace_lsb": 156,
            "description": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR. This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state. The following instructions are not counted: +//0 Writes to CONTEXTIDR_EL12 and CONTEXTIDR_EL2"
        },
        {
            "code": 16,
            "refs": [
                0
            ],
            "name": "BR_MIS_PRED",
            "architectural": false,
            "type": "UEVT",
            "subtype": "MISPREDICT",
            "component": "BPU",
            "event_bits": 1,
            "event_lsb": 14,
            "trace_lsb": 14,
            "description": "Mispredicted or not predicted branch speculatively executed. This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken"
        },
        {
            "code": 17,
            "refs": [
                0
            ],
            "name": "CPU_CYCLES",
            "architectural": false,
            "type": "CYCLE",
            "event_bits": 1,
            "event_lsb": 15,
            "trace_lsb": 15,
            "description": "Cycle"
        },
        {
            "code": 18,
            "refs": [
                0
            ],
            "name": "BR_PRED",
            "architectural": false,
            "type": "UEVT",
            "component": "BPU",
            "event_bits": 1,
            "event_lsb": 16,
            "trace_lsb": 16,
            "description": "Predictable branch speculatively executed. This event counts all predictable branches"
        },
        {
            "code": 19,
            "refs": [
                0
            ],
            "name": "MEM_ACCESS",
            "architectural": false,
            "type": "INS",
            "subtype": "ACCESS",
            "event_bits": 3,
            "event_lsb": 17,
            "trace_lsb": 17,
            "description": "Data memory access. This event counts memory accesses due to load or store instructions. The following instructions are not counted: +//0 Instruction fetches. +//0 Cache maintenance instructions. +//0 Translation table walks or prefetches. This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR"
        },
        {
            "code": 20,
            "refs": [
                0
            ],
            "name": "L1I_CACHE",
            "architectural": false,
            "type": "UEVT",
            "subtype": "ACCESS",
            "component": "L1I",
            "event_bits": 1,
            "event_lsb": 20,
            "trace_lsb": 20,
            "description": "Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache. The following instructions are not counted: +//0 Cache maintenance instructions. +//0 Non-cacheable accesses"
        },
        {
            "code": 21,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_WB",
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "event_bits": 1,
            "event_lsb": 21,
            "trace_lsb": 21,
            "description": "L1 data cache Write-Back. This event counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line evictions and snoops, including cache maintenance operations. The following instructions are not counted: +//0 Invalidations which do not result in data being transferred out of the L1. +//0 Full-line writes which write to L2 without writing L1, such as write streaming mode"
        },
        {
            "code": 22,
            "refs": [
                0
            ],
            "name": "L2D_CACHE",
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "event_bits": 3,
            "event_lsb": 22,
            "trace_lsb": 22,
            "description": "L2 data cache access. This event counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted"
        },
        {
            "code": 23,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_REFILL",
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L2",
            "event_bits": 3,
            "event_lsb": 25,
            "trace_lsb": 25,
            "description": "L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted"
        },
        {
            "code": 24,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_WB",
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "event_bits": 3,
            "event_lsb": 28,
            "trace_lsb": 28,
            "description": "L2 data cache write-back. This event counts any write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whether they cause an invalidation. Invalidations from the L2 which do not write data outside of the core and snoops which return data from the L1 are not counted"
        },
        {
            "code": 25,
            "refs": [
                0
            ],
            "name": "BUS_ACCESS",
            "architectural": false,
            "type": "UEVT",
            "component": "BUS",
            "event_bits": 2,
            "event_lsb": 31,
            "trace_lsb": 31,
            "description": "Bus access. This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR"
        },
        {
            "code": 26,
            "refs": [
                0
            ],
            "name": "MEMORY_ERROR",
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 33,
            "trace_lsb": 33,
            "description": "Local memory error. This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs"
        },
        {
            "code": 27,
            "refs": [
                0
            ],
            "name": "INST_SPEC",
            "architectural": false,
            "type": "UEVT",
            "event_bits": 3,
            "event_lsb": 34,
            "trace_lsb": 34,
            "description": "Operation speculatively executed"
        },
        {
            "code": 28,
            "refs": [
                0
            ],
            "name": "TTBR_WRITE_RETIRED",
            "architectural": true,
            "type": "INS",
            "event_bits": 1,
            "event_lsb": 37,
            "trace_lsb": 37,
            "description": "Instruction architecturally executed, condition code check pass, write to TTBR.This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state. The following instructions are not counted: +//0 Accesses to TTBR0_EL12/TTBR1_EL12 or TTBR0_EL2/ TTBR1_EL2"
        },
        {
            "code": 29,
            "refs": [
                0
            ],
            "name": "BUS_CYCLES",
            "architectural": false,
            "type": "UEVT",
            "component": "BUS",
            "event_bits": 1,
            "event_lsb": 38,
            "trace_lsb": 38,
            "description": "Bus cycles. This event duplicates CPU_CYCLES"
        },
        {
            "code": 30,
            "refs": [
                0
            ],
            "name": "CHAIN",
            "for_driver": true,
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 39,
            "trace_lsb": 39,
            "description": "For odd-numbered counters, increments the count by one for each overflow of the preceding even-numbered counter. For even-numbered counters, there is no increment"
        },
        {
            "code": 32,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_ALLOCATE",
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "event_bits": 2,
            "event_lsb": 40,
            "trace_lsb": 40,
            "description": "L2 data cache allocation without refill. This event counts any full cache line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate into L1"
        },
        {
            "code": 33,
            "refs": [
                0
            ],
            "name": "BR_RETIRED",
            "architectural": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 42,
            "trace_lsb": 42,
            "description": "Instruction architecturally executed, branch. This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches"
        },
        {
            "code": 34,
            "refs": [
                0
            ],
            "name": "BR_MIS_PRED_RETIRED",
            "architectural": false,
            "type": "UEVT",
            "subtype": "MISPREDICT",
            "component": "BPU",
            "event_bits": 1,
            "event_lsb": 43,
            "trace_lsb": 43,
            "description": "Instruction architecturally executed, mispredicted branch. This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush"
        },
        {
            "code": 35,
            "refs": [
                0
            ],
            "name": "STALL_FRONTEND",
            "architectural": false,
            "type": "CYCLE",
            "event_bits": 1,
            "event_lsb": 44,
            "trace_lsb": 44,
            "description": "No operation issued because of the frontend. The counter counts on any cycle when there are no fetched instructions available to dispatch"
        },
        {
            "code": 36,
            "refs": [
                0
            ],
            "name": "STALL_BACKEND",
            "architectural": false,
            "type": "CYCLE",
            "event_bits": 1,
            "event_lsb": 45,
            "trace_lsb": 45,
            "description": "No operation issued because of the backend. The counter counts on any cycle fetched instructions are not dispatched due to resource constraints"
        },
        {
            "code": 37,
            "refs": [
                0
            ],
            "name": "L1D_TLB",
            "architectural": false,
            "type": "UEVT",
            "component": "L1DTLB",
            "event_bits": 3,
            "event_lsb": 46,
            "trace_lsb": 46,
            "description": "Level 1 data TLB access. This event counts any load or store operation which accesses the data L1 TLB. If both a load and a store are executed on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled"
        },
        {
            "code": 38,
            "refs": [
                0
            ],
            "name": "L1I_TLB",
            "architectural": false,
            "type": "UEVT",
            "component": "L1ITLB",
            "event_bits": 1,
            "event_lsb": 168,
            "trace_lsb": 168,
            "description": "Level 1 instruction TLB access. This event counts any instruction fetch which accesses the instruction L1 TLB.This event counts regardless of whether the MMU is enabled"
        },
        {
            "code": 41,
            "refs": [
                0
            ],
            "name": "L3D_CACHE_ALLOCATE",
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L3",
            "event_bits": 1,
            "event_lsb": 157,
            "trace_lsb": 157,
            "description": "Attributable L3 data or unified cache allocation without refill. This event counts any full cache line write into the L3 cache which does not cause a linefill, including write-backs from L2 to L3 and full-line writes which do not allocate into L2"
        },
        {
            "code": 42,
            "refs": [
                0
            ],
            "name": "L3D_CACHE_REFILL",
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L3",
            "event_bits": 2,
            "event_lsb": 158,
            "trace_lsb": 158,
            "description": "Attributable Level 3 unified cache refill. This event counts for any cacheable read transaction returning data from the SCU for which the data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' transactions, even though they can be generated by store instructions"
        },
        {
            "code": 43,
            "refs": [
                0
            ],
            "name": "L3D_CACHE",
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L3",
            "event_bits": 1,
            "event_lsb": 160,
            "trace_lsb": 160,
            "description": "Attributable Level 3 unified cache access. This event counts for any cacheable read transaction returning data from the SCU, or for any cacheable write to the SCU"
        },
        {
            "code": 45,
            "refs": [
                0
            ],
            "name": "L2D_TLB_REFILL",
            "architectural": false,
            "type": "UEVT",
            "component": "L2TLB",
            "event_bits": 1,
            "event_lsb": 49,
            "trace_lsb": 49,
            "description": "Attributable L2 data or unified TLB refill. This event counts on any refill of the L2 TLB, caused by either an instruction or data access. This event does not count if the MMU is disabled"
        },
        {
            "code": 47,
            "refs": [
                0
            ],
            "name": "L2D_TLB",
            "architectural": false,
            "type": "UEVT",
            "component": "L2TLB",
            "event_bits": 2,
            "event_lsb": 50,
            "trace_lsb": 50,
            "description": "Attributable L2 data or unified TLB access. This event counts on any access to the L2 TLB (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled"
        },
        {
            "code": 49,
            "refs": [
                0
            ],
            "name": "REMOTE_ACCESS",
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 161,
            "trace_lsb": 161,
            "description": "Access to another socket in a multi-socket system"
        },
        {
            "code": 52,
            "refs": [
                0
            ],
            "name": "DTLB_WALK",
            "architectural": false,
            "type": "UEVT",
            "component": "L2TLB",
            "event_bits": 1,
            "event_lsb": 52,
            "trace_lsb": 52,
            "description": "Access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count"
        },
        {
            "code": 53,
            "refs": [
                0
            ],
            "name": "ITLB_WALK",
            "architectural": false,
            "type": "UEVT",
            "component": "L2TLB",
            "event_bits": 1,
            "event_lsb": 53,
            "trace_lsb": 53,
            "description": "Access to instruction TLB that caused a page table walk. This event counts on any instruction access which causes L2D_TLB_REFILL to count"
        },
        {
            "code": 54,
            "refs": [
                0
            ],
            "name": "LL_CACHE_RD",
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L1D",
            "event_bits": 2,
            "event_lsb": 162,
            "trace_lsb": 162,
            "description": "Last level cache access, read. +//0 If CPUECTLR.EXTLLC is set: This event counts any cacheable read transaction which returns a data source of 'interconnect cache'. +//0 If CPUECTLR.EXTLLC is not set: This event is a duplicate of the L*D_CACHE_RD event corresponding to the last level of cache implemented - L3D_CACHE_RD if both per-core L2 and cluster L3 are implemented, L2D_CACHE_RD if only one is implemented, or L1D_CACHE_RD if neither is implemented"
        },
        {
            "code": 55,
            "refs": [
                0
            ],
            "name": "LL_CACHE_MISS_RD",
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L1D",
            "event_bits": 2,
            "event_lsb": 164,
            "trace_lsb": 164,
            "description": "Last level cache miss, read. +//0 If CPUECTLR.EXTLLC is set: This event counts any cacheable read transaction which returns a data source of 'DRAM', 'remote' or 'inter-cluster peer'. +//0 If CPUECTLR.EXTLLC is not set: This event is a duplicate of the L*D_CACHE_REFILL_RD event corresponding to the last level of cache implemented - L3D_CACHE_REFILL_RD if both percore L2 and cluster L3 are implemented, L2D_CACHE_REFILL_RD if only one is implemented, or L1D_CACHE_REFILL_RD if neither is implemented"
        },
        {
            "code": 64,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L1D",
            "description": "L1 data cache access, read. This event counts any load operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL_RD event causes this event to count. The following instructions are not counted: +//0 Cache maintenance instructions and prefetches. +//0 Non-cacheable accesses"
        },
        {
            "code": 65,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_WR",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "event_bits": 2,
            "event_lsb": 56,
            "trace_lsb": 56,
            "description": "L1 data cache access, write. This event counts any store operation which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL_WR event causes this event to count. The following instructions are not counted: +//0 Cache maintenance instructions and prefetches. +//0 Non-cacheable accesses"
        },
        {
            "code": 66,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_REFILL_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L1D",
            "event_bits": 1,
            "event_lsb": 58,
            "trace_lsb": 58,
            "description": "L1 data cache refill, read. This event counts any load operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1. The following instructions are not counted: +//0 Cache maintenance instructions and prefetches. +//0 Non-cacheable accesses"
        },
        {
            "code": 67,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_REFILL_WR",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "event_bits": 1,
            "event_lsb": 59,
            "trace_lsb": 59,
            "description": "L1 data cache refill, write. This event counts any store operation which causes data to be read from outside the L1, including accesses which do not allocate into L1. The following instructions are not counted: +//0 Cache maintenance instructions and prefetches. +//0 Stores of an entire cache line, even if they make a coherency request outside the L1. +//0 Partial cache line writes which do not allocate into the L1 cache. +//0 Non-cacheable accesses"
        },
        {
            "code": 68,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_REFILL_INNER",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1D",
            "event_bits": 1,
            "event_lsb": 60,
            "trace_lsb": 60,
            "description": "L1 data cache refill, inner. This event counts any L1 D-cache linefill (as counted by L1D_CACHE_REFILL) which hits in the L2 cache, L3 cache or another core in the cluster"
        },
        {
            "code": 69,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_REFILL_OUTER",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1D",
            "event_bits": 1,
            "event_lsb": 61,
            "trace_lsb": 61,
            "description": "L1 data cache refill, outer. This event counts any L1 D-cache linefill (as counted by L1D_CACHE_REFILL) which does not hit in the L2 cache, L3 cache or another core in the cluster, and instead obtains data from outside the cluster"
        },
        {
            "code": 70,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_WB_VICTIM",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "event_bits": 1,
            "event_lsb": 62,
            "trace_lsb": 62,
            "description": "L1 data cache write-back, victim"
        },
        {
            "code": 71,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_WB_CLEAN",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "event_bits": 1,
            "event_lsb": 63,
            "trace_lsb": 63,
            "description": "L1 data cache write-back cleaning and coherency"
        },
        {
            "code": 72,
            "refs": [
                0
            ],
            "name": "L1D_CACHE_INVAL",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L1D",
            "event_bits": 1,
            "event_lsb": 64,
            "trace_lsb": 64,
            "description": "L1 data cache invalidate"
        },
        {
            "code": 76,
            "refs": [
                0
            ],
            "name": "L1D_TLB_REFILL_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L1DTLB",
            "event_bits": 1,
            "event_lsb": 65,
            "trace_lsb": 65,
            "description": "L1 data TLB refill, read"
        },
        {
            "code": 77,
            "refs": [
                0
            ],
            "name": "L1D_TLB_REFILL_WR",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L1DTLB",
            "event_bits": 1,
            "event_lsb": 66,
            "trace_lsb": 66,
            "description": "L1 data TLB refill, write"
        },
        {
            "code": 78,
            "refs": [
                0
            ],
            "name": "L1D_TLB_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L1DTLB",
            "event_bits": 2,
            "event_lsb": 67,
            "trace_lsb": 67,
            "description": "L1 data TLB access, read"
        },
        {
            "code": 79,
            "refs": [
                0
            ],
            "name": "L1D_TLB_WR",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L1DTLB",
            "event_bits": 2,
            "event_lsb": 69,
            "trace_lsb": 69,
            "description": "L1 data TLB access, write"
        },
        {
            "code": 80,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L2",
            "event_bits": 2,
            "event_lsb": 71,
            "trace_lsb": 71,
            "description": "L2 data cache access, read. This event counts any read transaction from L1 which looks up in the L2 cache. Snoops from outside the core are not counted"
        },
        {
            "code": 81,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_WR",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "event_bits": 2,
            "event_lsb": 73,
            "trace_lsb": 73,
            "description": "L2 data cache access, write. This event counts any write transaction from L1 which looks up in the L2 cache or any write-back from L1 which allocates into the L2 cache. Snoops from outside the core are not counted"
        },
        {
            "code": 82,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_REFILL_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L2",
            "event_bits": 2,
            "event_lsb": 75,
            "trace_lsb": 75,
            "description": "L2 data cache refill, read. This event counts any cacheable read transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted. Transactions such as ReadUnique are counted here as 'read' transactions, even though they can be generated by store instructions"
        },
        {
            "code": 83,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_REFILL_WR",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "event_bits": 2,
            "event_lsb": 77,
            "trace_lsb": 77,
            "description": "L2 data cache refill, write. This event counts any write transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted. Transactions such as ReadUnique are not counted as write transactions"
        },
        {
            "code": 86,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_WB_VICTIM",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "event_bits": 2,
            "event_lsb": 79,
            "trace_lsb": 79,
            "description": "L2 data cache write-back, victim"
        },
        {
            "code": 87,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_WB_CLEAN",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "event_bits": 2,
            "event_lsb": 81,
            "trace_lsb": 81,
            "description": "L2 data cache write-back, cleaning and coherency"
        },
        {
            "code": 88,
            "refs": [
                0
            ],
            "name": "L2D_CACHE_INVAL",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L2",
            "event_bits": 2,
            "event_lsb": 83,
            "trace_lsb": 83,
            "description": "L2 data cache invalidate"
        },
        {
            "code": 92,
            "refs": [
                0
            ],
            "name": "L2D_TLB_REFILL_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L2TLB",
            "event_bits": 1,
            "event_lsb": 85,
            "trace_lsb": 85,
            "description": "L2 data or unified TLB refill, read"
        },
        {
            "code": 93,
            "refs": [
                0
            ],
            "name": "L2D_TLB_REFILL_WR",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L2TLB",
            "event_bits": 1,
            "event_lsb": 86,
            "trace_lsb": 86,
            "description": "L2 data or unified TLB refill, write"
        },
        {
            "code": 94,
            "refs": [
                0
            ],
            "name": "L2D_TLB_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L2TLB",
            "event_bits": 2,
            "event_lsb": 87,
            "trace_lsb": 87,
            "description": "L2 data or unified TLB access, read"
        },
        {
            "code": 95,
            "refs": [
                0
            ],
            "name": "L2D_TLB_WR",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "component": "L2TLB",
            "event_bits": 1,
            "event_lsb": 89,
            "trace_lsb": 89,
            "description": "L2 data or unified TLB access, write"
        },
        {
            "code": 96,
            "refs": [
                0
            ],
            "name": "BUS_ACCESS_RD",
            "recommended": true,
            "impdef": true,
            "type": "UEVT",
            "component": "BUS",
            "event_bits": 1,
            "event_lsb": 90,
            "trace_lsb": 90,
            "description": "Bus access read. This event counts for every beat of data transferred over the read data channel between the core and the SCU"
        },
        {
            "code": 97,
            "refs": [
                0
            ],
            "name": "BUS_ACCESS_WR",
            "recommended": true,
            "impdef": true,
            "type": "UEVT",
            "component": "BUS",
            "event_bits": 1,
            "event_lsb": 91,
            "trace_lsb": 91,
            "description": "Bus access write. This event counts for every beat of data transferred over the write data channel between the core and the SCU"
        },
        {
            "code": 102,
            "refs": [
                0
            ],
            "name": "MEM_ACCESS_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "subtype": "READ",
            "event_bits": 2,
            "event_lsb": 92,
            "trace_lsb": 92,
            "description": "Data memory access, read. This event counts memory accesses due to load instructions. The following instructions are not counted: +//0 Instruction fetches. +//0 Cache maintenance instructions. +//0 Translation table walks. +//0 Prefetches"
        },
        {
            "code": 103,
            "refs": [
                0
            ],
            "name": "MEM_ACCESS_WR",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "subtype": "WRITE",
            "event_bits": 2,
            "event_lsb": 94,
            "trace_lsb": 94,
            "description": "Data memory access, write. This event counts memory accesses due to store instructions. The following instructions are not counted: +//0 Instruction fetches. +//0 Cache maintenance instructions. +//0 Translation table walks. +//0 Prefetches"
        },
        {
            "code": 104,
            "refs": [
                0
            ],
            "name": "UNALIGNED_LD_SPEC",
            "recommended": true,
            "impdef": true,
            "type": "UEVT",
            "event_bits": 2,
            "event_lsb": 96,
            "trace_lsb": 96,
            "description": "Unaligned access, read"
        },
        {
            "code": 105,
            "refs": [
                0
            ],
            "name": "UNALIGNED_ST_SPEC",
            "recommended": true,
            "impdef": true,
            "type": "UEVT",
            "event_bits": 2,
            "event_lsb": 98,
            "trace_lsb": 98,
            "description": "Unaligned access, write"
        },
        {
            "code": 106,
            "refs": [
                0
            ],
            "name": "UNALIGNED_LDST_SPEC",
            "recommended": true,
            "impdef": true,
            "type": "UEVT",
            "event_bits": 3,
            "event_lsb": 100,
            "trace_lsb": 100,
            "description": "Unaligned access"
        },
        {
            "code": 108,
            "refs": [
                0
            ],
            "name": "LDREX_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 103,
            "trace_lsb": 103,
            "description": "Exclusive operation speculatively executed, LDREX or LDX"
        },
        {
            "code": 109,
            "refs": [
                0
            ],
            "name": "STREX_PASS_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 104,
            "trace_lsb": 104,
            "description": "Exclusive operation speculatively executed, STREX or STX pass"
        },
        {
            "code": 110,
            "refs": [
                0
            ],
            "name": "STREX_FAIL_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 105,
            "trace_lsb": 105,
            "description": "Exclusive operation speculatively executed, STREX or STX fail"
        },
        {
            "code": 111,
            "refs": [
                0
            ],
            "name": "STREX_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 106,
            "trace_lsb": 106,
            "description": "Exclusive operation speculatively executed, STREX or STX"
        },
        {
            "code": 112,
            "refs": [
                0
            ],
            "name": "LD_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 3,
            "event_lsb": 107,
            "trace_lsb": 107,
            "description": "Operation speculatively executed, load"
        },
        {
            "code": 113,
            "refs": [
                0
            ],
            "name": "ST_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 3,
            "event_lsb": 110,
            "trace_lsb": 110,
            "description": "Operation speculatively executed, store"
        },
        {
            "code": 114,
            "refs": [
                0
            ],
            "name": "LDST_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 2,
            "event_lsb": 113,
            "trace_lsb": 113,
            "description": "Operation speculatively executed, load or store. This event counts the sum of LD_SPEC and ST_SPEC"
        },
        {
            "code": 115,
            "refs": [
                0
            ],
            "name": "DP_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 3,
            "event_lsb": 115,
            "trace_lsb": 115,
            "description": "Operation speculatively executed, integer data-processing"
        },
        {
            "code": 116,
            "refs": [
                0
            ],
            "name": "ASE_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "event_bits": 3,
            "event_lsb": 118,
            "trace_lsb": 118,
            "description": "Operation speculatively executed, Advanced SIMD instruction"
        },
        {
            "code": 117,
            "refs": [
                0
            ],
            "name": "VFP_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "event_bits": 3,
            "event_lsb": 121,
            "trace_lsb": 121,
            "description": "Operation speculatively executed, floating-point instruction"
        },
        {
            "code": 118,
            "refs": [
                0
            ],
            "name": "PC_WRITE_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 2,
            "event_lsb": 124,
            "trace_lsb": 124,
            "description": "Operation speculatively executed, software change of the PC"
        },
        {
            "code": 119,
            "refs": [
                0
            ],
            "name": "CRYPTO_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "event_bits": 3,
            "event_lsb": 126,
            "trace_lsb": 126,
            "description": "Operation speculatively executed, Cryptographic instruction"
        },
        {
            "code": 120,
            "refs": [
                0
            ],
            "name": "BR_IMMED_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 129,
            "trace_lsb": 129,
            "description": "Branch speculatively executed, immediate branch"
        },
        {
            "code": 121,
            "refs": [
                0
            ],
            "name": "BR_RETURN_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 130,
            "trace_lsb": 130,
            "description": "Branch speculatively executed, procedure return"
        },
        {
            "code": 122,
            "refs": [
                0
            ],
            "name": "BR_INDIRECT_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 131,
            "trace_lsb": 131,
            "description": "Branch speculatively executed, indirect branch"
        },
        {
            "code": 124,
            "refs": [
                0
            ],
            "name": "ISB_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 1,
            "event_lsb": 132,
            "trace_lsb": 132,
            "description": "Barrier speculatively executed, ISB"
        },
        {
            "code": 125,
            "refs": [
                0
            ],
            "name": "DSB_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 2,
            "event_lsb": 133,
            "trace_lsb": 133,
            "description": "Barrier speculatively executed, DSB"
        },
        {
            "code": 126,
            "refs": [
                0
            ],
            "name": "DMB_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 2,
            "event_lsb": 135,
            "trace_lsb": 135,
            "description": "Barrier speculatively executed, DMB"
        },
        {
            "code": 129,
            "refs": [
                0
            ],
            "name": "EXC_UNDEF",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 137,
            "trace_lsb": 137,
            "description": "Counts the number of undefined exceptions taken locally"
        },
        {
            "code": 130,
            "refs": [
                0
            ],
            "name": "EXC_SVC",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 138,
            "trace_lsb": 138,
            "description": "Exception taken locally, Supervisor Call"
        },
        {
            "code": 131,
            "refs": [
                0
            ],
            "name": "EXC_PABORT",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 139,
            "trace_lsb": 139,
            "description": "Exception taken locally, Instruction Abort"
        },
        {
            "code": 132,
            "refs": [
                0
            ],
            "name": "EXC_DABORT",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 140,
            "trace_lsb": 140,
            "description": "Exception taken locally, Data Abort and SError"
        },
        {
            "code": 134,
            "refs": [
                0
            ],
            "name": "EXC_IRQ",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 141,
            "trace_lsb": 141,
            "description": "Exception taken locally, IRQ"
        },
        {
            "code": 135,
            "refs": [
                0
            ],
            "name": "EXC_FIQ",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 142,
            "trace_lsb": 142,
            "description": "Exception taken locally, FIQ"
        },
        {
            "code": 136,
            "refs": [
                0
            ],
            "name": "EXC_SMC",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 143,
            "trace_lsb": 143,
            "description": "Exception taken locally, Secure Monitor Call"
        },
        {
            "code": 138,
            "refs": [
                0
            ],
            "name": "EXC_HVC",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 144,
            "trace_lsb": 144,
            "description": "Exception taken locally, Hypervisor Call"
        },
        {
            "code": 139,
            "refs": [
                0
            ],
            "name": "EXC_TRAP_PABORT",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 145,
            "trace_lsb": 145,
            "description": "Exception taken, Instruction Abort not taken locally"
        },
        {
            "code": 140,
            "refs": [
                0
            ],
            "name": "EXC_TRAP_DABORT",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 146,
            "trace_lsb": 146,
            "description": "Exception taken, Data Abort or SError not taken locally"
        },
        {
            "code": 141,
            "refs": [
                0
            ],
            "name": "EXC_TRAP_OTHER",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 147,
            "trace_lsb": 147,
            "description": "Exception taken, Other traps not taken locally"
        },
        {
            "code": 142,
            "refs": [
                0
            ],
            "name": "EXC_TRAP_IRQ",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 148,
            "trace_lsb": 148,
            "description": "Exception taken, IRQ not taken locally"
        },
        {
            "code": 143,
            "refs": [
                0
            ],
            "name": "EXC_TRAP_FIQ",
            "recommended": true,
            "impdef": true,
            "type": "EXC",
            "event_bits": 1,
            "event_lsb": 149,
            "trace_lsb": 149,
            "description": "Exception taken, FIQ not taken locally"
        },
        {
            "code": 144,
            "refs": [
                0
            ],
            "name": "RC_LD_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 3,
            "event_lsb": 150,
            "trace_lsb": 150,
            "description": "Release consistency operation speculatively executed, load-acquire"
        },
        {
            "code": 145,
            "refs": [
                0
            ],
            "name": "RC_ST_SPEC",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "event_bits": 3,
            "event_lsb": 153,
            "trace_lsb": 153,
            "description": "Release consistency operation speculatively executed, store-release"
        },
        {
            "code": 160,
            "refs": [
                0
            ],
            "trm_name": "L3_CACHE_RD",
            "name": "L3D_CACHE_RD",
            "recommended": true,
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L3",
            "event_bits": 1,
            "event_lsb": 166,
            "trace_lsb": 166,
            "description": "L3 cache read"
        },
        {
            "code": 512,
            "refs": [
                1
            ],
            "name": "BR_MIS_PRED_RS",
            "impdef": true,
            "type": "UEVT",
            "subtype": "MISPREDICT",
            "component": "BPU",
            "description": "Branch mispredict restricted. The counter counts each correction to the predicted program flow that occurs because of a misprediction or no prediction, and relates to switches between Restricted and Executive"
        },
        {
            "code": 513,
            "refs": [
                1
            ],
            "name": "BR_MIS_PRED_C64",
            "impdef": true,
            "type": "UEVT",
            "subtype": "MISPREDICT",
            "component": "BPU",
            "description": "Branch mispredict C64. The counter counts each correction to the predicted program flow that occurs because of a misprediction or no prediction, and relates to switches between A64 and C64"
        },
        {
            "code": 514,
            "refs": [
                1
            ],
            "name": "BR_MIS_PRED_SYS",
            "impdef": true,
            "type": "UEVT",
            "subtype": "MISPREDICT",
            "component": "BPU",
            "description": "Branch mispredict system permission. The counter counts each correction to the predicted program flow that occurs because of a misprediction or no prediction, and relates to System permission"
        },
        {
            "code": 515,
            "refs": [
                1
            ],
            "name": "PCCRF_FULL",
            "impdef": true,
            "architectural": false,
            "type": "CYCLE",
            "description": "PCC register file full. The counter counts every cycle counted by the CPU_CYCLES event on which no operation was issued because the PCC write tracking register file was full"
        },
        {
            "code": 516,
            "refs": [
                1
            ],
            "name": "EXECUTIVE_ENTRY",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "description": "Entry to Executive, Operations Speculatively Executed. The counter counts speculatively executed operations that cause an entry into Executive"
        },
        {
            "code": 517,
            "refs": [
                1
            ],
            "name": "EXECUTIVE_EXIT",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "description": "Exit from Executive, Operations Speculatively Executed. The counter counts speculatively executed operations that cause an exit from Executive"
        },
        {
            "code": 518,
            "refs": [
                1
            ],
            "name": "INST_SPEC_A64",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Instructions in A64, Operations Speculatively Executed. The counter counts speculatively executed operations due to all instructions in A64"
        },
        {
            "code": 519,
            "refs": [
                1
            ],
            "name": "INST_SPEC_C64",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Instructions in C64, Operations Speculatively Executed. The counter counts speculatively executed operations due to all instructions in C64"
        },
        {
            "code": 520,
            "refs": [
                1
            ],
            "name": "CID_EL0_WRITE_RETIRED",
            "impdef": true,
            "architectural": true,
            "type": "INS",
            "description": "Instruction architecturally executed, Write to CID_EL0. The counter counts architecturally executed instructions which write to the Compartment ID Register"
        },
        {
            "code": 521,
            "refs": [
                1
            ],
            "name": "DDC_WRITE_RETIRED",
            "impdef": true,
            "architectural": true,
            "type": "INS",
            "description": "Instruction architecturally executed, Write to DDC_ELx, RDDC_EL0. The counter counts architecturally executed instructions which write to any Default Data Capability"
        },
        {
            "code": 522,
            "refs": [
                1
            ],
            "name": "DDC_READ_SPEC",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "description": "Read from DDC_ELx, RDDC_EL0, Operations Speculatively Executed. The counter counts speculatively executed operations which read from any Default Data Capability"
        },
        {
            "code": 523,
            "refs": [
                1
            ],
            "name": "INST_SPEC_CVTD",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "CVTD Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to the following instructions: +ICI CVTD (not flag setting): Convert pointer to capability offset from DDC. +ICI CVTD (flag setting): Convert capability to pointer offset from DDC, setting flags. +ICI CVTDZ: Convert pointer to capability offset from DDC, with null capability from zero semantics"
        },
        {
            "code": 526,
            "refs": [
                1
            ],
            "name": "INST_SPEC_SCBNDS_NONEXACT",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "SCBNDS or SCBNDSE Instructions which do not set exact bounds, Operations Speculatively Executed. The counter counts speculatively executed operations due to any of the following instructions not succeeding in setting the requested bounds exactly: +ICI SCBNDS (register): Set Bounds (register). +ICI SCBNDS (immediate): Set Bounds (immediate). +ICI SCBNDSE: Set Bounds Exact"
        },
        {
            "code": 527,
            "refs": [
                1
            ],
            "name": "CDBM_SET_SC",
            "impdef": true,
            "type": "UEVT",
            "description": "SC set due to CDBM. The counter counts each setting of the permission bit to write Capability Tags to memory in a translation table entry which is due to the CDBM bit being set"
        },
        {
            "code": 528,
            "refs": [
                1
            ],
            "name": "CAP_LD_SPEC",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Capability Load Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Capability load instructions"
        },
        {
            "code": 529,
            "refs": [
                1
            ],
            "name": "CAP_ST_SPEC",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Capability Store Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Capability store instructions"
        },
        {
            "code": 530,
            "refs": [
                1
            ],
            "name": "CAP_ALT_LD_SPEC",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Alternate Base Capability Load Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base Capability load instructions"
        },
        {
            "code": 531,
            "refs": [
                1
            ],
            "name": "CAP_ALT_ST_SPEC",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Alternate Base Capability Store Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base Capability store instructions"
        },
        {
            "code": 532,
            "refs": [
                1
            ],
            "name": "ALT_LD_SPEC",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Alternate Base Load Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base load instructions"
        },
        {
            "code": 533,
            "refs": [
                1
            ],
            "name": "ALT_ST_SPEC",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Alternate Base Store Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base store instructions"
        },
        {
            "code": 534,
            "refs": [
                1
            ],
            "name": "LDCT_SPEC",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "LDCT Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Load Tags instructions"
        },
        {
            "code": 535,
            "refs": [
                1
            ],
            "name": "LDCT_NO_CAP_SPEC",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "LDCT Instructions When Capability Tags are Zero, Operations Speculatively Executed. The counter counts speculatively executed operations due to Load Capability Tags instructions where the Capability Tags to be loaded are all zero"
        },
        {
            "code": 536,
            "refs": [
                1
            ],
            "name": "DC_ZVA_RET",
            "impdef": true,
            "architectural": true,
            "type": "INS",
            "description": "Data Cache Zero. The counter counts architecturally executed DC ZVA instructions"
        },
        {
            "code": 538,
            "refs": [
                1
            ],
            "name": "LDCT_REFILL",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1D",
            "description": "Data cache refill due to LDCT, Operations Speculatively Executed. The counter counts each access counted by L1D_CACHE that causes a demand refill of any cache due to execution of an LDCT instruction"
        },
        {
            "code": 539,
            "refs": [
                1
            ],
            "name": "STCT_REFILL",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1D",
            "description": "Data cache refill due to STCT, Operations Speculatively Executed. The counter counts each access counted by L1D_CACHE that causes a demand refill of any cache due to execution of an STCT instruction"
        },
        {
            "code": 540,
            "refs": [
                1
            ],
            "name": "L1D_CACHE_RD_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L1D",
            "description": "Attributable Level 1 data cache access, read, valid capability. The counter counts each access counted by L1D_CACHE_RD which loaded a valid capability"
        },
        {
            "code": 541,
            "refs": [
                1
            ],
            "name": "L1D_CACHE_WR_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "description": "Attributable Level 1 data cache access, write, valid capability. The counter counts each access counted by L1D_CACHE_WR which stored a valid capability"
        },
        {
            "code": 542,
            "refs": [
                1
            ],
            "name": "L1D_CACHE_WB_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "description": "Attributable Level 1 data cache write-back, valid capability. The counter counts each access counted by L1D_CACHE_WB where at least one valid capability was present in the cache line"
        },
        {
            "code": 543,
            "refs": [
                1
            ],
            "name": "L1D_CACHE_REFILL_RD_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1D",
            "description": "Attributable Level 1 data cache refill, capability. The counter counts each access counted by L1D_CACHE_REFILL_RD where at least one valid capability was present in the cache line"
        },
        {
            "code": 544,
            "refs": [
                1
            ],
            "name": "L1D_CACHE_REFILL_WR_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1D",
            "description": "Attributable Level 1 data cache refill, capability. The counter counts each access counted by L1D_CACHE_REFILL_WR where at least one valid capability was present in the cache line"
        },
        {
            "code": 545,
            "refs": [
                1
            ],
            "name": "L1D_CACHE_REFILL_INNER_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1D",
            "description": "Attributable Level 1 data cache refill, inner, valid capability. The counter counts each access counted by L1D_CACHE_REFILL_INNER where at least one valid capability was present in the cache line"
        },
        {
            "code": 546,
            "refs": [
                1
            ],
            "name": "L1D_CACHE_REFILL_OUTER_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L1D",
            "description": "Attributable Level 1 data cache refill, outer, valid capability. The counter counts each access counted by L1D_CACHE_REFILL_OUTER where at least one valid capability was present in the cache line"
        },
        {
            "code": 547,
            "refs": [
                1
            ],
            "name": "L1D_CACHE_WB_VICTIM_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "description": "Attributable Level 1 data cache Write-Back, victim, valid capability. The counter counts each access counted by L1D_CACHE_WB_VICTIM where at least one valid capability was present in the cache line"
        },
        {
            "code": 548,
            "refs": [
                1
            ],
            "name": "L1D_CACHE_WB_CLEAN_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L1D",
            "description": "Attributable Level 1 data cache Write-Back, cleaning, and coherency, valid capability. The counter counts each access counted by L1D_CACHE_WB_CLEAN where at least one valid capability was present in the cache line"
        },
        {
            "code": 550,
            "refs": [
                1
            ],
            "name": "L2D_CACHE_RD_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "READ",
            "component": "L2",
            "description": "Attributable Level 2 data cache access, read, valid capability. The counter counts each access counted by L2D_CACHE_RD which loaded a valid Capability"
        },
        {
            "code": 551,
            "refs": [
                1
            ],
            "name": "L2D_CACHE_WR_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "description": "Attributable Level 2 data cache access, write, valid capability. The counter counts each access counted by L2D_CACHE_WR which stored a valid Capability"
        },
        {
            "code": 552,
            "refs": [
                1
            ],
            "name": "L2D_CACHE_REFILL_RD_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "REFILL",
            "component": "L2",
            "description": "Attributable Level 2 data cache refill, valid capability. The counter counts each access counted by L2D_CACHE_REFILL_RD where at least one valid capability was present in the cache line"
        },
        {
            "code": 554,
            "refs": [
                1
            ],
            "name": "L2D_CACHE_WB_VICTIM_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "description": "Attributable Level 2 data cache Write-Back, victim, valid capability. The counter counts each access counted by L2D_CACHE_WB_VICTIM where at least one valid capability was present in the cache line"
        },
        {
            "code": 555,
            "refs": [
                1
            ],
            "name": "L2D_CACHE_WB_CLEAN_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "WRITE",
            "component": "L2",
            "description": "Attributable Level 2 data cache Write-Back, cleaning and coherency, valid capability. The counter counts each access counted by L2D_CACHE_WB_CLEAN where at least one valid capability was present in the cache line"
        },
        {
            "code": 556,
            "refs": [
                1
            ],
            "name": "L2D_CACHE_INVAL_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "UEVT",
            "subtype": "ACCESS",
            "component": "L2",
            "description": "Attributable Level 2 data cache invalidate, valid capability. The counter counts each access counted by L2D_CACHE_INVAL where at least one valid capability was present in the cache line"
        },
        {
            "code": 557,
            "refs": [
                1
            ],
            "name": "BUS_ACCESS_RD_CTAG",
            "impdef": true,
            "type": "UEVT",
            "component": "BUS",
            "description": "Bus access, read, valid capability. The counter counts each access counted by BUS_ACCESS_RD where a Capability Tag was set in at least one beat of the access"
        },
        {
            "code": 558,
            "refs": [
                1
            ],
            "name": "BUS_ACCESS_WR_CTAG",
            "impdef": true,
            "type": "UEVT",
            "component": "BUS",
            "description": "Bus access, write, valid capability. The counter counts each access counted by BUS_ACCESS_WR where a Capability Tag was set in at least one beat of the access"
        },
        {
            "code": 559,
            "refs": [
                1
            ],
            "name": "CNT_ST_ZERO_BYTE",
            "impdef": true,
            "architectural": true,
            "type": "INS",
            "description": "Store of zeros. In combination with the CNT_ST_ZERO_16TH_BYTE, the counter counts the number of bytes written by architecturally executed store instructions, not including DC ZVA where only zeros are stored and not including stores which store 16 bytes of zero"
        },
        {
            "code": 560,
            "refs": [
                1
            ],
            "name": "CNT_ST_ZERO_16_BYTES",
            "impdef": true,
            "architectural": true,
            "type": "INS",
            "description": "Store of zeros, 16 byte stores. The counter counts when 16 bytes of zero are written by an architecturally executed store instruction"
        },
        {
            "code": 563,
            "refs": [
                1
            ],
            "name": "MEM_ACCESS_RD_CTAG",
            "impdef": true,
            "type": "UEVT",
            "description": "Data memory access, read, valid capability. The counter counts each access counted by MEM_ACCESS_RD where a Capability Tag was set in at least one part of the access"
        },
        {
            "code": 564,
            "refs": [
                1
            ],
            "name": "MEM_ACCESS_WR_CTAG",
            "impdef": true,
            "type": "UEVT",
            "description": "Data memory access, write, valid capability. The counter counts each access counted by MEM_ACCESS_WR where a Capability Tag was set in at least one part of the access"
        },
        {
            "code": 565,
            "refs": [
                1
            ],
            "name": "CAP_MEM_ACCESS_RD",
            "impdef": true,
            "type": "INS",
            "description": "Data memory access, read, capability. The counter counts each access counted by MEM_ACCESS_RD due to an instruction which loads a capability. It is not sensitive to the validity of the capability"
        },
        {
            "code": 566,
            "refs": [
                1
            ],
            "name": "CAP_MEM_ACCESS_WR",
            "impdef": true,
            "type": "INS",
            "description": "Data memory access, write, capability. The counter counts each access counted by MEM_ACCESS_WR due to an instruction which stores a capability. It is not sensitive to the validity of the capability"
        },
        {
            "code": 567,
            "refs": [
                1
            ],
            "name": "INST_SPEC_RESTRICTED",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Instructions in Restricted, Operations Speculatively Executed. The counter counts speculatively executed operations due to all instructions in Restricted"
        },
        {
            "code": 568,
            "refs": [
                1
            ],
            "name": "LD_CAP_PERM_CLR_CTAG",
            "impdef": true,
            "architectural": false,
            "type": "INS",
            "description": "Load permission cleared, Operations Speculatively Executed. The counter counts speculatively executed operations due to load instructions where the capability tag is cleared due to the operation having been performed without LoadCap permission"
        }
    ]
}