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i2c_api.c
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i2c_api.c
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015-2021, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "mbed_assert.h"
#include "i2c_api.h"
#include "platform/mbed_wait_api.h"
#if DEVICE_I2C
#include <string.h>
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "i2c_device.h" // family specific defines
#include "mbed_error.h"
#include "platform/mbed_power_mgmt.h"
#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO
/** @defgroup I2C_DEVICE_Private_Constants I2C_DEVICE Private Constants
* @{
*/
#ifndef I2C_VALID_TIMING_NBR
#define I2C_VALID_TIMING_NBR 128U
#endif
#define I2C_SPEED_FREQ_STANDARD 0U /* 100 kHz */
#define I2C_SPEED_FREQ_FAST 1U /* 400 kHz */
#define I2C_SPEED_FREQ_FAST_PLUS 2U /* 1 MHz */
#define I2C_ANALOG_FILTER_DELAY_MIN 50U /* ns */
#define I2C_ANALOG_FILTER_DELAY_MAX 260U /* ns */
#define I2C_USE_ANALOG_FILTER 1U
#define I2C_DIGITAL_FILTER_COEF 0U
#define I2C_PRESC_MAX 16U
#define I2C_SCLDEL_MAX 16U
#define I2C_SDADEL_MAX 16U
#define I2C_SCLH_MAX 256U
#define I2C_SCLL_MAX 256U
#define SEC2NSEC 1000000000UL
/**
* @}
*/
/** @defgroup I2C_DEVICE_Private_Types I2C_DEVICE Private Types
* @{
*/
typedef struct {
uint32_t freq; /* Frequency in Hz */
uint32_t freq_min; /* Minimum frequency in Hz */
uint32_t freq_max; /* Maximum frequency in Hz */
uint32_t hddat_min; /* Minimum data hold time in ns */
uint32_t vddat_max; /* Maximum data valid time in ns */
uint32_t sudat_min; /* Minimum data setup time in ns */
uint32_t lscl_min; /* Minimum low period of the SCL clock in ns */
uint32_t hscl_min; /* Minimum high period of SCL clock in ns */
uint32_t trise; /* Rise time in ns */
uint32_t tfall; /* Fall time in ns */
uint32_t dnf; /* Digital noise filter coefficient */
} I2C_Charac_t;
typedef struct {
uint32_t presc; /* Timing prescaler */
uint32_t tscldel; /* SCL delay */
uint32_t tsdadel; /* SDA delay */
uint32_t sclh; /* SCL high period */
uint32_t scll; /* SCL low period */
} I2C_Timings_t;
/**
* @}
*/
/** @defgroup I2C_DEVICE_Private_Constants I2C_DEVICE Private Constants
* @{
*/
static const I2C_Charac_t I2C_Charac[] = {
[I2C_SPEED_FREQ_STANDARD] =
{
.freq = 100000,
.freq_min = 80000,
.freq_max = 120000,
.hddat_min = 0,
.vddat_max = 3450,
.sudat_min = 250,
.lscl_min = 4700,
.hscl_min = 4000,
.trise = 640,
.tfall = 20,
.dnf = I2C_DIGITAL_FILTER_COEF,
},
[I2C_SPEED_FREQ_FAST] =
{
.freq = 400000,
.freq_min = 320000,
.freq_max = 480000,
.hddat_min = 0,
.vddat_max = 900,
.sudat_min = 100,
.lscl_min = 1300,
.hscl_min = 600,
.trise = 250,
.tfall = 100,
.dnf = I2C_DIGITAL_FILTER_COEF,
},
[I2C_SPEED_FREQ_FAST_PLUS] =
{
.freq = 1000000,
.freq_min = 800000,
.freq_max = 1200000,
.hddat_min = 0,
.vddat_max = 450,
.sudat_min = 50,
.lscl_min = 500,
.hscl_min = 260,
.trise = 60,
.tfall = 100,
.dnf = I2C_DIGITAL_FILTER_COEF,
},
};
/**
* @}
*/
/** @defgroup I2C_DEVICE_Private_Variables I2C_DEVICE Private Variables
* @{
*/
static I2C_Timings_t I2c_valid_timing[I2C_VALID_TIMING_NBR];
static uint32_t I2c_valid_timing_nbr = 0;
#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO
#ifndef DEBUG_STDIO
# define DEBUG_STDIO 0
#endif
#if DEBUG_STDIO
# include <stdio.h>
# define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
#else
# define DEBUG_PRINTF(...) {}
#endif
#if DEVICE_I2C_ASYNCH
#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
#else
#define I2C_S(obj) (struct i2c_s *) (obj)
#endif
/* Family specific description for I2C */
#define I2C_NUM (5)
static I2C_HandleTypeDef *i2c_handles[I2C_NUM];
/* Timeout values are based on core clock and I2C clock.
The BYTE_TIMEOUT is computed as twice the number of cycles it would
take to send 10 bits over I2C. Most Flags should take less than that.
This is for immediate FLAG or ACK check.
*/
#define BYTE_TIMEOUT ((SystemCoreClock / obj_s->hz) * 2 * 10)
/* Timeout values based on I2C clock.
The BYTE_TIMEOUT_US is computed as 3x the time in us it would
take to send 10 bits over I2C. Most Flags should take less than that.
This is for complete transfers check.
*/
#define BYTE_TIMEOUT_US ((SystemCoreClock / obj_s->hz) * 3 * 10)
/* Timeout values for flags and events waiting loops. These timeouts are
not based on accurate values, they just guarantee that the application will
not remain stuck if the I2C communication is corrupted.
*/
#ifdef TARGET_STM32H7
#define FLAG_TIMEOUT ((int)0x1100)
#else
#define FLAG_TIMEOUT ((int)0x1000)
#endif
#ifdef I2C_IP_VERSION_V1
#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#endif
#define SLAVE_MODE_RECEIVE 1
#define SLAVE_MODE_LISTEN 2
#define DEFAULT_SLAVE_MODE SLAVE_MODE_LISTEN
/* Declare i2c_init_internal to be used in this file */
void i2c_init_internal(i2c_t *obj, const i2c_pinmap_t *pinmap);
/* GENERIC INIT and HELPERS FUNCTIONS */
#if defined(I2C1_BASE)
static void i2c1_irq(void)
{
I2C_HandleTypeDef *handle = i2c_handles[0];
HAL_I2C_EV_IRQHandler(handle);
HAL_I2C_ER_IRQHandler(handle);
}
#endif
#if defined(I2C2_BASE)
static void i2c2_irq(void)
{
I2C_HandleTypeDef *handle = i2c_handles[1];
HAL_I2C_EV_IRQHandler(handle);
HAL_I2C_ER_IRQHandler(handle);
}
#endif
#if defined(I2C3_BASE)
static void i2c3_irq(void)
{
I2C_HandleTypeDef *handle = i2c_handles[2];
HAL_I2C_EV_IRQHandler(handle);
HAL_I2C_ER_IRQHandler(handle);
}
#endif
#if defined(I2C4_BASE)
static void i2c4_irq(void)
{
I2C_HandleTypeDef *handle = i2c_handles[3];
HAL_I2C_EV_IRQHandler(handle);
HAL_I2C_ER_IRQHandler(handle);
}
#endif
#if defined(I2C5_BASE) // STM32H7
static void i2c5_irq(void)
{
I2C_HandleTypeDef *handle = i2c_handles[4];
HAL_I2C_EV_IRQHandler(handle);
HAL_I2C_ER_IRQHandler(handle);
}
#endif
#if defined(FMPI2C1_BASE) // STM32F4
static void i2c5_irq(void)
{
I2C_HandleTypeDef *handle = i2c_handles[4];
HAL_I2C_EV_IRQHandler(handle);
HAL_I2C_ER_IRQHandler(handle);
}
#endif
void i2c_ev_err_enable(i2c_t *obj, uint32_t handler)
{
struct i2c_s *obj_s = I2C_S(obj);
IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
/* default prio in master case is set to 2 */
uint32_t prio = 2;
/* Set up ITs using IRQ and handler tables */
NVIC_SetVector(irq_event_n, handler);
NVIC_SetVector(irq_error_n, handler);
#if DEVICE_I2CSLAVE
/* Set higher priority to slave device than master.
* In case a device makes use of both master and slave, the
* slave needs higher responsiveness.
*/
if (obj_s->slave) {
prio = 1;
}
#endif
NVIC_SetPriority(irq_event_n, prio);
NVIC_SetPriority(irq_error_n, prio);
NVIC_EnableIRQ(irq_event_n);
NVIC_EnableIRQ(irq_error_n);
}
void i2c_ev_err_disable(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
HAL_NVIC_DisableIRQ(irq_event_n);
HAL_NVIC_DisableIRQ(irq_error_n);
}
uint32_t i2c_get_irq_handler(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
uint32_t handler = 0;
switch (obj_s->index) {
#if defined(I2C1_BASE)
case 0:
handler = (uint32_t)&i2c1_irq;
break;
#endif
#if defined(I2C2_BASE)
case 1:
handler = (uint32_t)&i2c2_irq;
break;
#endif
#if defined(I2C3_BASE)
case 2:
handler = (uint32_t)&i2c3_irq;
break;
#endif
#if defined(I2C4_BASE)
case 3:
handler = (uint32_t)&i2c4_irq;
break;
#endif
#if defined(I2C5_BASE)
case 4:
handler = (uint32_t)&i2c5_irq;
break;
#endif
#if defined(FMPI2C1_BASE)
case 4:
handler = (uint32_t)&i2c5_irq;
break;
#endif
}
i2c_handles[obj_s->index] = handle;
return handler;
}
void i2c_hw_reset(i2c_t *obj)
{
int timeout;
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
// wait before reset
timeout = BYTE_TIMEOUT;
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
#if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined I2C1_BASE
if (obj_s->i2c == I2C_1) {
__HAL_RCC_I2C1_FORCE_RESET();
__HAL_RCC_I2C1_RELEASE_RESET();
}
#endif
#if defined I2C2_BASE
if (obj_s->i2c == I2C_2) {
__HAL_RCC_I2C2_FORCE_RESET();
__HAL_RCC_I2C2_RELEASE_RESET();
}
#endif
#if defined I2C3_BASE
if (obj_s->i2c == I2C_3) {
__HAL_RCC_I2C3_FORCE_RESET();
__HAL_RCC_I2C3_RELEASE_RESET();
}
#endif
#if defined I2C4_BASE
if (obj_s->i2c == I2C_4) {
__HAL_RCC_I2C4_FORCE_RESET();
__HAL_RCC_I2C4_RELEASE_RESET();
}
#endif
#if defined I2C5_BASE
if (obj_s->i2c == I2C_5) {
__HAL_RCC_I2C5_FORCE_RESET();
__HAL_RCC_I2C5_RELEASE_RESET();
}
#endif
#if defined FMPI2C1_BASE
if (obj_s->i2c == FMPI2C_1) {
__HAL_RCC_FMPI2C1_FORCE_RESET();
__HAL_RCC_FMPI2C1_RELEASE_RESET();
}
#endif
#if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */
}
void i2c_sw_reset(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
/* SW reset procedure:
* PE must be kept low during at least 3 APB clock cycles
* in order to perform the software reset.
* This is ensured by writing the following software sequence:
* - Write PE=0
* - Check PE=0
* - Write PE=1.
*/
handle->Instance->CR1 &= ~I2C_CR1_PE;
while (handle->Instance->CR1 & I2C_CR1_PE);
handle->Instance->CR1 |= I2C_CR1_PE;
}
void i2c_init_internal(i2c_t *obj, const i2c_pinmap_t *pinmap)
{
struct i2c_s *obj_s = I2C_S(obj);
#ifdef I2C_IP_VERSION_V2
/* These variables are initialized with 0, to overcome possiblity of
garbage assignment */
obj_s->current_hz = 0;
obj_s->handle.Init.Timing = 0;
#endif
/* Determine the I2C to use */
if (pinmap != NULL) {
obj_s->sda = pinmap->sda_pin;
obj_s->scl = pinmap->scl_pin;
#if STATIC_PINMAP_READY
obj_s->sda_func = pinmap->sda_function;
obj_s->scl_func = pinmap->scl_function;
#endif
obj_s->i2c = (I2CName)pinmap->peripheral;
MBED_ASSERT(obj_s->i2c != (I2CName)NC);
}
#if defined I2C1_BASE
// Enable I2C1 clock and pinout if not done
if (obj_s->i2c == I2C_1) {
obj_s->index = 0;
__HAL_RCC_I2C1_CLK_ENABLE();
// Configure I2C pins
obj_s->event_i2cIRQ = I2C1_EV_IRQn;
obj_s->error_i2cIRQ = I2C1_ER_IRQn;
#if defined(TARGET_STM32WL) || defined(TARGET_STM32WB)
/* In Stop2 mode, I2C1 and I2C2 instances are powered down (only I2C3 register content is kept) */
sleep_manager_lock_deep_sleep();
#endif
}
#endif
#if defined I2C2_BASE
// Enable I2C2 clock and pinout if not done
if (obj_s->i2c == I2C_2) {
obj_s->index = 1;
__HAL_RCC_I2C2_CLK_ENABLE();
obj_s->event_i2cIRQ = I2C2_EV_IRQn;
obj_s->error_i2cIRQ = I2C2_ER_IRQn;
#if defined(TARGET_STM32WL)
/* In Stop2 mode, I2C1 and I2C2 instances are powered down (only I2C3 register content is kept) */
sleep_manager_lock_deep_sleep();
#endif
}
#endif
#if defined I2C3_BASE
// Enable I2C3 clock and pinout if not done
if (obj_s->i2c == I2C_3) {
obj_s->index = 2;
__HAL_RCC_I2C3_CLK_ENABLE();
obj_s->event_i2cIRQ = I2C3_EV_IRQn;
obj_s->error_i2cIRQ = I2C3_ER_IRQn;
}
#endif
#if defined I2C4_BASE
// Enable I2C4 clock and pinout if not done
if (obj_s->i2c == I2C_4) {
obj_s->index = 3;
__HAL_RCC_I2C4_CLK_ENABLE();
obj_s->event_i2cIRQ = I2C4_EV_IRQn;
obj_s->error_i2cIRQ = I2C4_ER_IRQn;
}
#endif
#if defined I2C5_BASE
// Enable I2C5 clock and pinout if not done
if (obj_s->i2c == I2C_5) {
obj_s->index = 4;
__HAL_RCC_I2C5_CLK_ENABLE();
obj_s->event_i2cIRQ = I2C5_EV_IRQn;
obj_s->error_i2cIRQ = I2C5_ER_IRQn;
}
#endif
#if defined FMPI2C1_BASE
// Enable I2C3 clock and pinout if not done
if (obj_s->i2c == FMPI2C_1) {
obj_s->index = 4;
__HAL_RCC_FMPI2C1_CLK_ENABLE();
obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
}
#endif
// Configure I2C pins
#if STATIC_PINMAP_READY
pin_function(obj_s->sda, obj_s->sda_func);
pin_function(obj_s->scl, obj_s->scl_func);
#else
pinmap_pinout(obj_s->sda, PinMap_I2C_SDA);
pinmap_pinout(obj_s->scl, PinMap_I2C_SCL);
#endif
pin_mode(obj_s->sda, OpenDrainNoPull);
pin_mode(obj_s->scl, OpenDrainNoPull);
// I2C configuration
// Default hz value used for timeout computation
if (!obj_s->hz) {
obj_s->hz = 100000; // 100 kHz per default
}
// Reset to clear pending flags if any
i2c_hw_reset(obj);
i2c_frequency(obj, obj_s->hz);
#ifdef I2C_IP_VERSION_V2
obj_s->current_hz = obj_s->hz;
#endif
#if DEVICE_I2CSLAVE
// I2C master by default
obj_s->slave = 0;
obj_s->pending_slave_tx_master_rx = 0;
obj_s->pending_slave_rx_maxter_tx = 0;
#endif
// I2C Xfer operation init
obj_s->event = 0;
obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
#ifdef I2C_IP_VERSION_V2
obj_s->pending_start = 0;
#endif
}
void i2c_deinit_internal(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
i2c_hw_reset(obj);
HAL_I2C_DeInit(&(obj_s->handle));
#if defined I2C1_BASE
if (obj_s->i2c == I2C_1) {
__HAL_RCC_I2C1_CLK_DISABLE();
#if defined(TARGET_STM32WL) || defined(TARGET_STM32WB)
sleep_manager_unlock_deep_sleep();
#endif
}
#endif
#if defined I2C2_BASE
if (obj_s->i2c == I2C_2) {
__HAL_RCC_I2C2_CLK_DISABLE();
#if defined(TARGET_STM32WL)
sleep_manager_unlock_deep_sleep();
#endif
}
#endif
#if defined I2C3_BASE
if (obj_s->i2c == I2C_3) {
__HAL_RCC_I2C3_CLK_DISABLE();
}
#endif
#if defined I2C4_BASE
if (obj_s->i2c == I2C_4) {
__HAL_RCC_I2C4_CLK_DISABLE();
}
#endif
#if defined I2C5_BASE
if (obj_s->i2c == I2C_5) {
__HAL_RCC_I2C5_CLK_DISABLE();
}
#endif
#if defined FMPI2C1_BASE
if (obj_s->i2c == FMPI2C_1) {
__HAL_RCC_FMPI2C1_CLK_DISABLE();
}
#endif
pin_function(obj_s->sda, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0));
pin_function(obj_s->scl, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0));
obj_s->sda = NC;
obj_s->scl = NC;
obj_s->i2c = (I2CName)NC;
}
#if STATIC_PINMAP_READY
#define I2C_INIT_DIRECT i2c_init_direct
void i2c_init_direct(i2c_t *obj, const i2c_pinmap_t *pinmap)
#else
#define I2C_INIT_DIRECT _i2c_init_direct
static void _i2c_init_direct(i2c_t *obj, const i2c_pinmap_t *pinmap)
#endif
{
memset(obj, 0, sizeof(*obj));
i2c_init_internal(obj, pinmap);
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
int peripheral = (int)pinmap_merge(i2c_sda, i2c_scl);
int sda_function = (int)pinmap_find_function(sda, PinMap_I2C_SDA);
int scl_function = (int)pinmap_find_function(scl, PinMap_I2C_SCL);
const i2c_pinmap_t explicit_i2c_pinmap = {peripheral, sda, sda_function, scl, scl_function};
I2C_INIT_DIRECT(obj, &explicit_i2c_pinmap);
}
void i2c_free(i2c_t *obj)
{
i2c_deinit_internal(obj);
}
void i2c_frequency(i2c_t *obj, int hz)
{
int timeout;
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
// wait before init
timeout = BYTE_TIMEOUT;
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
#ifdef I2C_IP_VERSION_V1
handle->Init.ClockSpeed = hz;
handle->Init.DutyCycle = I2C_DUTYCYCLE_2;
#endif
#ifdef I2C_IP_VERSION_V2
// Enable the Fast Mode Plus capability
if (hz == 1000000) {
#if defined(I2C1_BASE) && defined(I2C_FASTMODEPLUS_I2C1) // sometimes I2C_FASTMODEPLUS_I2Cx is define even if not supported by the chip
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) || defined(SYSCFG_CFGR1_I2C1_FMP) || defined(SYSCFG_PMC_I2C1_FMP) || defined(SYSCFG_PMCR_I2C1_FMP) || defined(SYSCFG_CFGR2_I2C1_FMP)
if (obj_s->i2c == I2C_1) {
HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
}
#endif
#endif
#if defined(I2C2_BASE) && defined(I2C_FASTMODEPLUS_I2C2) // sometimes I2C_FASTMODEPLUS_I2Cx is define even if not supported by the chip
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) || defined(SYSCFG_CFGR1_I2C2_FMP) || defined(SYSCFG_PMC_I2C2_FMP) || defined(SYSCFG_PMCR_I2C2_FMP) || defined(SYSCFG_CFGR2_I2C2_FMP)
if (obj_s->i2c == I2C_2) {
HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C2);
}
#endif
#endif
#if defined(I2C3_BASE) && defined (I2C_FASTMODEPLUS_I2C3) // sometimes I2C_FASTMODEPLUS_I2Cx is define even if not supported by the chip
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C3) || defined(SYSCFG_CFGR1_I2C3_FMP) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMCR_I2C3_FMP) || defined(SYSCFG_CFGR2_I2C3_FMP)
if (obj_s->i2c == I2C_3) {
HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3);
}
#endif
#endif
#if defined(I2C4_BASE) && defined (I2C_FASTMODEPLUS_I2C4) // sometimes I2C_FASTMODEPLUS_I2Cx is define even if not supported by the chip
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C4) || defined(SYSCFG_CFGR1_I2C4_FMP) || defined(SYSCFG_PMC_I2C4_FMP) || defined(SYSCFG_PMCR_I2C4_FMP) || defined(SYSCFG_CFGR2_I2C4_FMP)
if (obj_s->i2c == I2C_4) {
HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C4);
}
#endif
#endif
#if defined(I2C5_BASE) && defined (I2C_FASTMODEPLUS_I2C5) // sometimes I2C_FASTMODEPLUS_I2Cx is define even if not supported by the chip
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C5) || defined(SYSCFG_CFGR1_I2C5_FMP) || defined(SYSCFG_PMC_I2C5_FMP) || defined(SYSCFG_PMCR_I2C5_FMP) || defined(SYSCFG_CFGR2_I2C5_FMP)
if (obj_s->i2c == I2C_5) {
HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C5);
}
#endif
#endif
}
#endif //I2C_IP_VERSION_V2
/*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
#if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)
if (obj_s->i2c == I2C_1) {
__HAL_RCC_I2C1_CONFIG(I2CAPI_I2C1_CLKSRC);
}
#endif
#if defined(I2C2_BASE) && defined(__HAL_RCC_I2C2_CONFIG)
if (obj_s->i2c == I2C_2) {
__HAL_RCC_I2C2_CONFIG(I2CAPI_I2C2_CLKSRC);
}
#endif
#if defined(I2C3_BASE) && defined(__HAL_RCC_I2C3_CONFIG)
if (obj_s->i2c == I2C_3) {
__HAL_RCC_I2C3_CONFIG(I2CAPI_I2C3_CLKSRC);
}
#endif
#if defined(I2C4_BASE) && defined(__HAL_RCC_I2C4_CONFIG)
if (obj_s->i2c == I2C_4) {
__HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
}
#endif
#if defined(I2C5_BASE) && defined(__HAL_RCC_I2C5_CONFIG)
if (obj_s->i2c == I2C_5) {
__HAL_RCC_I2C5_CONFIG(I2CAPI_I2C5_CLKSRC);
}
#endif
#if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */
#ifdef I2C_ANALOGFILTER_ENABLE
/* Enable the Analog I2C Filter */
HAL_I2CEx_ConfigAnalogFilter(handle, I2C_ANALOGFILTER_ENABLE);
#endif
#ifdef I2C_IP_VERSION_V2
/* Only predefined timing for below frequencies are supported */
MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
/* Derives I2C timing value with respect to I2C input clock source speed
and I2C bus frequency requested. "Init.Timing" is passed to this function to
reduce multiple computation of timing value which there by reduces CPU load.
*/
handle->Init.Timing = i2c_get_timing(obj_s->i2c, handle->Init.Timing, \
obj_s->current_hz, hz);
/* Only non-zero timing value is supported */
MBED_ASSERT(handle->Init.Timing != 0);
/* hz value is stored for computing timing value next time */
obj_s->current_hz = hz;
#endif // I2C_IP_VERSION_V2
// I2C configuration
handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
handle->Init.OwnAddress1 = 0;
handle->Init.OwnAddress2 = 0;
#ifdef I2C_IP_VERSION_V2
handle->Init.OwnAddress2Masks = I2C_OA2_NOMASK;
#endif
HAL_I2C_Init(handle);
/* store frequency for timeout computation */
obj_s->hz = hz;
}
i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c)
{
/* Aim of the function is to get i2c_s pointer using hi2c pointer */
/* Highly inspired from magical linux kernel's "container_of" */
/* (which was not directly used since not compatible with IAR toolchain) */
struct i2c_s *obj_s;
i2c_t *obj;
obj_s = (struct i2c_s *)((char *)hi2c - offsetof(struct i2c_s, handle));
obj = (i2c_t *)((char *)obj_s - offsetof(i2c_t, i2c));
return (obj);
}
void i2c_reset(i2c_t *obj)
{
/* As recommended in i2c_api.h, mainly send stop */
i2c_stop(obj);
/* then re-init */
i2c_init_internal(obj, NULL);
}
/*
* UNITARY APIS.
* For very basic operations, direct registers access is needed
* There are 2 different IPs version that need to be supported
*/
#ifdef I2C_IP_VERSION_V1
int i2c_start(i2c_t *obj)
{
int timeout;
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
// Clear Acknowledge failure flag
__HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
// Wait the STOP condition has been previously correctly sent
// This timeout can be avoid in some specific cases by simply clearing the STOP bit
timeout = FLAG_TIMEOUT;
while ((handle->Instance->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) {
if ((timeout--) == 0) {
return 1;
}
}
// Generate the START condition
handle->Instance->CR1 |= I2C_CR1_START;
// Wait the START condition has been correctly sent
timeout = FLAG_TIMEOUT;
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
if ((timeout--) == 0) {
return 1;
}
}
return 0;
}
int i2c_stop(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
// Generate the STOP condition
i2c->CR1 |= I2C_CR1_STOP;
/* In case of mixed usage of the APIs (unitary + SYNC)
* re-init HAL state
*/
if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
i2c_init_internal(obj, NULL);
}
return 0;
}
int i2c_byte_read(i2c_t *obj, int last)
{
int timeout;
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
if (last) {
// Don't acknowledge the last byte
handle->Instance->CR1 &= ~I2C_CR1_ACK;
} else {
// Acknowledge the byte
handle->Instance->CR1 |= I2C_CR1_ACK;
}
// Wait until the byte is received
timeout = FLAG_TIMEOUT;
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
if ((timeout--) == 0) {
return -1;
}
}
return (int)handle->Instance->DR;
}
int i2c_byte_write(i2c_t *obj, int data)
{
int timeout;
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
handle->Instance->DR = (uint8_t)data;
// Wait until the byte (might be the address) is transmitted
timeout = FLAG_TIMEOUT;
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
(__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
(__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) {
if ((timeout--) == 0) {
return 2;
}
}
if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET) {
__HAL_I2C_CLEAR_ADDRFLAG(handle);
}
return 1;
}
#endif //I2C_IP_VERSION_V1
#ifdef I2C_IP_VERSION_V2
int i2c_start(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
/* This I2C IP doesn't */
obj_s->pending_start = 1;
return 0;
}
int i2c_stop(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
int timeout = FLAG_TIMEOUT;
#if DEVICE_I2CSLAVE
if (obj_s->slave) {
/* re-init slave when stop is requested */
i2c_init_internal(obj, NULL);
return 0;
}
#endif
// Ensure the transmission is started before sending a stop
if ((handle->Instance->CR2 & (uint32_t)I2C_CR2_RD_WRN) == 0) {
timeout = FLAG_TIMEOUT;
while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXIS)) {
if ((timeout--) == 0) {
return I2C_ERROR_BUS_BUSY;
}
}
}
// Generate the STOP condition
handle->Instance->CR2 = I2C_CR2_STOP;
timeout = FLAG_TIMEOUT;
while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_STOPF)) {
if ((timeout--) == 0) {
return I2C_ERROR_BUS_BUSY;
}
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_STOPF);
/* Erase slave address, this wiil be used as a marker
* to know when we need to prepare next start */
handle->Instance->CR2 &= ~I2C_CR2_SADD;
/*
* V2 IP is meant for automatic STOP, not user STOP
* SW reset the IP state machine before next transaction
*/
i2c_sw_reset(obj);
/* In case of mixed usage of the APIs (unitary + SYNC)
* re-init HAL state */
if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
i2c_init_internal(obj, NULL);
}
return 0;
}
int i2c_byte_read(i2c_t *obj, int last)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
int timeout = FLAG_TIMEOUT;
uint32_t tmpreg = handle->Instance->CR2;
char data;
#if DEVICE_I2CSLAVE
if (obj_s->slave) {
return i2c_slave_read(obj, &data, 1);
}
#endif
/* Then send data when there's room in the TX fifo */
if ((tmpreg & I2C_CR2_RELOAD) != 0) {
while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
if ((timeout--) == 0) {
DEBUG_PRINTF("timeout in i2c_byte_read\r\n");
return -1;
}
}
}
if (last) {
/* Disable Address Acknowledge */
tmpreg = tmpreg & (~I2C_CR2_RELOAD);
tmpreg |= I2C_CR2_NACK | (I2C_CR2_NBYTES & (1 << 16));
} else {
/* Enable reload mode as we don't know how many bytes will be sent */
/* and set transfer size to 1 */
tmpreg |= I2C_CR2_RELOAD | (I2C_CR2_NBYTES & (1 << 16));
}
/* Set the prepared configuration */
handle->Instance->CR2 = tmpreg;
timeout = FLAG_TIMEOUT;
while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE)) {
if ((timeout--) == 0) {
return -1;
}
}
/* Then Get Byte */
data = handle->Instance->RXDR;
return data;
}