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MK66FN2M0xxx18.sct
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MK66FN2M0xxx18.sct
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#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
/*
** ###################################################################
** Processors: MK66FN2M0VLQ18
** MK66FN2M0VMD18
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
** Version: rev. 3.0, 2015-03-25
** Build: b170214
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define __ram_vector_table__ 1
#if (defined(__ram_vector_table__))
#define __ram_vector_table_size__ 0x00000400
#else
#define __ram_vector_table_size__ 0x00000000
#endif
#if !defined(MBED_APP_START)
#define MBED_APP_START 0
#elif MBED_APP_START > 0 && MBED_APP_START < 0x410
#error MBED_APP_START too small and will overwrite interrupts and flash config
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x200000
#endif
#define m_interrupts_start MBED_APP_START
#define m_interrupts_size 0x00000400
#if MBED_APP_START == 0
#define m_flash_config_start MBED_APP_START + 0x400
#define m_flash_config_size 0x00000010
#define m_text_start MBED_APP_START + 0x410
#define m_text_size MBED_APP_SIZE - 0x410
#else
#define m_text_start MBED_APP_START + 0x400
#define m_text_size MBED_APP_SIZE - 0x400
#endif
#define m_interrupts_ram_start 0x1FFF0000
#define m_interrupts_ram_size __ram_vector_table_size__
#define m_crash_report_ram_start (m_interrupts_ram_start + m_interrupts_ram_size)
#define m_crash_report_ram_size (0x100)
#define m_data_start (m_crash_report_ram_start + m_crash_report_ram_size)
#define m_data_size (0x00010000 - (m_interrupts_ram_size+m_crash_report_ram_size))
#define m_data_2_start 0x20000000
#define m_data_2_size 0x00030000
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#endif
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
#endif
LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
#if MBED_APP_START == 0
ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
* (FlashConfig)
}
#endif
ER_IROM1 m_text_start m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
#if (defined(__ram_vector_table__))
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
}
#else
VECTOR_RAM m_interrupts_start EMPTY 0 {
}
#endif
RW_m_crash_data m_crash_report_ram_start EMPTY m_crash_report_ram_size { ; RW data
}
RW_m_data m_data_start m_data_size { ; RW data
.ANY2 (+RW +ZI)
}
RW_m_data_2 m_data_2_start m_data_2_size { ; RW data
.ANY1 (+RW +ZI)
}
RW_IRAM1 ImageLimit(RW_m_data_2) EMPTY 0 {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (m_data_2_start + m_data_2_size - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
}
ARM_LIB_STACK m_data_2_start+m_data_2_size EMPTY -Stack_Size { ; Stack region growing down
}
}