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FPGA_Project.gise
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FPGA_Project.gise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FPGA_Project.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="ALU_32b_TB_isim_beh.exe"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="data_memory_TB_isim_beh.exe"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="incrementer_32b_TB_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="incrementer_32b_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="instruction_memory_TB_isim_beh.exe"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="mips.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="mips.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="mips.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="mips.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="mips.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="mips.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="mips.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="mips.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="mips.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="mips.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="mips.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="mips.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="mips.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mips.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="mips.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="mips.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="mips.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="mips.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="mips.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="mips.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="mips.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="mips.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="mips.xst"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mips_TB_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="mips_TB_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="mips_TB_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="mips_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="mips_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="mips_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="mips_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="mips_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="mips_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="mips_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="mips_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="mips_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="mips_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="mips_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="mips_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="mips_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="mips_xst.xrpt"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="mux_32b_2b1_TB_isim_beh.exe"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="register_32b_TB_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="register_bank_TB_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="sign_etend_TB_isim_beh.exe"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1595778306" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1595778306">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1595779641" xil_pn:in_ck="7610056486141849945" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1595779641">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ALU_32b.v"/>
<outfile xil_pn:name="ALU_32b_TB.v"/>
<outfile xil_pn:name="C:/Users/Ahmadreza/Desktop/Project/ALU_control.v"/>
<outfile xil_pn:name="C:/Users/Ahmadreza/Desktop/Project/Control.v"/>
<outfile xil_pn:name="data_memory.v"/>
<outfile xil_pn:name="data_memory_TB.v"/>
<outfile xil_pn:name="incrementer_32b.v"/>
<outfile xil_pn:name="incrementer_32b_TB.v"/>
<outfile xil_pn:name="instruction_memory.v"/>
<outfile xil_pn:name="instruction_memory_TB.v"/>
<outfile xil_pn:name="mips.v"/>
<outfile xil_pn:name="mips_TB.v"/>
<outfile xil_pn:name="mux_32b_2b1.v"/>
<outfile xil_pn:name="mux_32b_2b1_TB.v"/>
<outfile xil_pn:name="register_32b.v"/>
<outfile xil_pn:name="register_32b_TB.v"/>
<outfile xil_pn:name="register_bank.v"/>
<outfile xil_pn:name="register_bank_TB.v"/>
<outfile xil_pn:name="sign_etend_TB.v"/>
<outfile xil_pn:name="sign_extend.v"/>
</transform>
<transform xil_pn:end_ts="1595778306" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="3043718950712007045" xil_pn:start_ts="1595778306">
<status xil_pn:value="SuccessfullyRun"/>
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<transform xil_pn:end_ts="1595778306" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-138615160015234237" xil_pn:start_ts="1595778306">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1595778306" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2741032113507398338" xil_pn:start_ts="1595778306">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="ALU_32b.v"/>
<outfile xil_pn:name="ALU_32b_TB.v"/>
<outfile xil_pn:name="C:/Users/Ahmadreza/Desktop/Project/ALU_control.v"/>
<outfile xil_pn:name="C:/Users/Ahmadreza/Desktop/Project/Control.v"/>
<outfile xil_pn:name="data_memory.v"/>
<outfile xil_pn:name="data_memory_TB.v"/>
<outfile xil_pn:name="incrementer_32b.v"/>
<outfile xil_pn:name="incrementer_32b_TB.v"/>
<outfile xil_pn:name="instruction_memory.v"/>
<outfile xil_pn:name="instruction_memory_TB.v"/>
<outfile xil_pn:name="mips.v"/>
<outfile xil_pn:name="mips_TB.v"/>
<outfile xil_pn:name="mux_32b_2b1.v"/>
<outfile xil_pn:name="mux_32b_2b1_TB.v"/>
<outfile xil_pn:name="register_32b.v"/>
<outfile xil_pn:name="register_32b_TB.v"/>
<outfile xil_pn:name="register_bank.v"/>
<outfile xil_pn:name="register_bank_TB.v"/>
<outfile xil_pn:name="sign_etend_TB.v"/>
<outfile xil_pn:name="sign_extend.v"/>
</transform>
<transform xil_pn:end_ts="1595779645" xil_pn:in_ck="7610056486141849945" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6891810596916714359" xil_pn:start_ts="1595779641">
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<outfile xil_pn:name="mips_TB_beh.prj"/>
<outfile xil_pn:name="mips_TB_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1595779645" xil_pn:in_ck="3991144049843678323" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7827127055245136236" xil_pn:start_ts="1595779645">
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<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="mips_TB_isim_beh.wdb"/>
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<transform xil_pn:end_ts="1596214593" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1596214593">
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<transform xil_pn:end_ts="1596214593" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3083755636328485294" xil_pn:start_ts="1596214593">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1596214593" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2741032113507398338" xil_pn:start_ts="1596214593">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1596214593" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1596214593">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1596214593" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-108373080525765968" xil_pn:start_ts="1596214593">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="mips_TB_beh.prj"/>
<outfile xil_pn:name="mips_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
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</transform>
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<outfile xil_pn:name="mips.par"/>
<outfile xil_pn:name="mips.ptwx"/>
<outfile xil_pn:name="mips.unroutes"/>
<outfile xil_pn:name="mips.xpi"/>
<outfile xil_pn:name="mips_pad.csv"/>
<outfile xil_pn:name="mips_pad.txt"/>
<outfile xil_pn:name="mips_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1596220345" xil_pn:in_ck="4785535742428" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="5341574683187206424" xil_pn:start_ts="1596220333">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="mips.bgn"/>
<outfile xil_pn:name="mips.bit"/>
<outfile xil_pn:name="mips.drc"/>
<outfile xil_pn:name="mips.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1596220346" xil_pn:in_ck="4785535729574" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1596220345">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1596220312" xil_pn:in_ck="-4991445578779779711" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1596220306">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="mips.twr"/>
<outfile xil_pn:name="mips.twx"/>
</transform>
</transforms>
</generated_project>