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fuse.log
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fuse.log
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Running: G:\program\xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o G:/program/xilinx/FPGA_Project/mips_TB_isim_beh.exe -prj G:/program/xilinx/FPGA_Project/mips_TB_beh.prj work.mips_TB work.glbl
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/sign_extend.v" into library work
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/register_bank.v" into library work
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/register_32b.v" into library work
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/mux_32b_2b1.v" into library work
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/instruction_memory.v" into library work
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/incrementer_32b.v" into library work
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/data_memory.v" into library work
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/ALU_32b.v" into library work
Analyzing Verilog file "C:/Users/Ahmadreza/Desktop/Project/Control.v" into library work
Analyzing Verilog file "C:/Users/Ahmadreza/Desktop/Project/ALU_control.v" into library work
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/mips.v" into library work
Analyzing Verilog file "G:/program/xilinx/FPGA_Project/mips_TB.v" into library work
Analyzing Verilog file "G:/program/xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Compiling module register_32b
Compiling module instruction_memory
Compiling module Control
Compiling module sign_extend
Compiling module incrementer_32b
Compiling module mux_32b_2b1
Compiling module register_bank
Compiling module ALU_32b
Compiling module ALU_control
Compiling module data_memory
Compiling module mips
Compiling module mips_TB
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 4 sub-compilation(s) to finish...
Compiled 13 Verilog Units
Built simulation executable G:/program/xilinx/FPGA_Project/mips_TB_isim_beh.exe
Fuse Memory Usage: 27808 KB
Fuse CPU Usage: 561 ms