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sign_etend_TB.v
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sign_etend_TB.v
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:07:35 07/24/2020
// Design Name: sign_extend
// Module Name: G:/program/xilinx/FPGA_Project/sign_etend_TB.v
// Project Name: FPGA_Project
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sign_extend
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sign_etend_TB;
// Inputs
reg [15:0] data_in;
// Outputs
wire [31:0] data_out;
// Instantiate the Unit Under Test (UUT)
sign_extend uut (
.data_in(data_in),
.data_out(data_out)
);
initial begin
// Initialize Inputs
data_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
data_in = 32;
#50
data_in = 128;
#50
data_in = -120;
#50
data_in = 0;
end
endmodule