This documentation intends to describe both the Alogic language, and the Alogic compiler which translates the Alogic language to Verilog. The sections can be read in linear order to provide an introduction to Alogic.
A zero configuration online compiler playground is available for experimentation. The reader is encouraged to try the examples in the documentation and inspect the resulting Verilog output.
- Basic concepts and examples
- Compilation model
- Design entities
- Data types and simple variables
- Expression typing rules
- Literal values
- Ports
- Parameters and constants
- Finite State Machines
- Statements
- Control flow conversion
- Expressions
- Networks
- Pipelines
- Distributed memories
- SRAMs
- Assertions
- Built-in functions
- The 'using' directive
- The import mechanism
- Compile time code generation
- Foreign function interface
- Verilog interoperability
- List of keywords
- Formal grammar
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