Ques1: Full Adder Ques2: Mux_4x1 Ques3: 1 bit Comprator Ques4: Full adder using Half Adder Ques5: mux4x1_using Vector Ques6: Logic gate using mux2x1
Code7:- Verilog code for $display,$monitor and Strobe: https://edaplayground.com/x/89mj
Code8: Verilog Code for Equality Oprator https://edaplayground.com/x/NWMp
Code10 Equality and Inequality_operator.v https://edaplayground.com/x/VRjh
Code11 Case Equality and Inequality_operator.v https://edaplayground.com/x/vin5
Code12 reg and wire datatypes.v https://edaplayground.com/x/Xh28
Code13 reg_datatype.v https://edaplayground.com/x/Sxmc
Code14 Drive reg time multipletime.v https://edaplayground.com/x/q8c6
Code15 Drive WIRE type multipletime.v https://edaplayground.com/x/wbxi
Code16 Inter and Intra assignment Delay.v https://edaplayground.com/x/T8KU
Code18 Task.v https://edaplayground.com/x/ix8z
Code19 Task have Output_port.v https://edaplayground.com/x/YnVX
Code20 Case, Casex and casez.v https://edaplayground.com/x/TwV4