controller_tb.vcd

$date
	Fri Apr 16 16:11:58 2021
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module controller_tb $end
$var wire 1 ! trigger_2 $end
$var wire 1 " trigger_1 $end
$var wire 4 # slave_out_2 [3:0] $end
$var wire 4 $ slave_out_1 [3:0] $end
$var wire 1 % done_2 $end
$var wire 1 & done_1 $end
$var reg 1 ' clk $end
$var reg 1 ( rst_n $end
$var reg 1 ) start $end
$scope module control $end
$var wire 1 ' clk $end
$var wire 1 ( rst_n $end
$var wire 1 ) start $end
$var wire 1 ! trigger_2 $end
$var wire 1 " trigger_1 $end
$var wire 1 % done_2 $end
$var wire 1 & done_1 $end
$var reg 2 * CS [1:0] $end
$var reg 2 + NS [1:0] $end
$upscope $end
$scope module one $end
$var wire 1 ' clk $end
$var wire 1 ( rst_n $end
$var wire 1 " slave_en $end
$var wire 1 & slave_done $end
$var reg 4 , slave_out [3:0] $end
$upscope $end
$scope module two $end
$var wire 1 ' clk $end
$var wire 1 ( rst_n $end
$var wire 1 ! slave_en $end
$var wire 1 % slave_done $end
$var reg 4 - slave_out [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
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