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rt2880_eth.c
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rt2880_eth.c
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#include <common.h>
#include <command.h>
#if defined (CONFIG_CMD_NET) && defined(CONFIG_RT2880_ETH)
#include <malloc.h>
#include <net.h>
#include <rt_mmap.h>
#include <miiphy.h>
#include <asm/errno.h>
#if defined (CONFIG_RTL8367)
#include "rtl8367c/include/smi.h"
#include "rtl8367c/include/port.h"
#include "rtl8367c/include/rtk_switch.h"
#include "rtl8367c/include/rtl8367c_asicdrv_port.h"
#endif
#if defined (GE_MII_FORCE_100) || defined (GE_RVMII_FORCE_100)
#define MAC_TO_100SW_MODE
#elif defined (GE_MII_AN) || defined (GE_RMII_AN)
#define MAC_TO_100PHY_MODE
#elif defined (GE_RGMII_AN) || defined (GE_RGMII_INTERNAL_P0_AN) || defined (GE_RGMII_INTERNAL_P4_AN)
#define MAC_TO_GIGAPHY_MODE
#elif defined (GE_RGMII_FORCE_1000) || defined (GE_TRGMII_FORCE_2600)
#define MAC_TO_MT7530_MODE
#endif
#undef DEBUG
#define BIT(x) ((1 << x))
/* bits range: for example BITS(16,23) = 0xFF0000
* ==> (BIT(m)-1) = 0x0000FFFF ~(BIT(m)-1) => 0xFFFF0000
* ==> (BIT(n+1)-1) = 0x00FFFFFF
*/
#define BITS(m,n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n)))
/* ====================================== */
//GDMA1 uni-cast frames destination port
#define GDM_UFRC_P_CPU ((u32)(~(0x7 << 12)))
#define GDM_UFRC_P_GDMA1 (1 << 12)
#define GDM_UFRC_P_GDMA2 (2 << 12)
#define GDM_UFRC_P_DROP (7 << 12)
//GDMA1 broad-cast MAC address frames
#define GDM_BFRC_P_CPU ((u32)(~(0x7 << 8)))
#define GDM_BFRC_P_GDMA1 (1 << 8)
#define GDM_BFRC_P_GDMA2 (2 << 8)
#define GDM_BFRC_P_PPE (6 << 8)
#define GDM_BFRC_P_DROP (7 << 8)
//GDMA1 multi-cast MAC address frames
#define GDM_MFRC_P_CPU ((u32)(~(0x7 << 4)))
#define GDM_MFRC_P_GDMA1 (1 << 4)
#define GDM_MFRC_P_GDMA2 (2 << 4)
#define GDM_MFRC_P_PPE (6 << 4)
#define GDM_MFRC_P_DROP (7 << 4)
//GDMA1 other MAC address frames destination port
#define GDM_OFRC_P_CPU ((u32)(~(0x7)))
#define GDM_OFRC_P_GDMA1 1
#define GDM_OFRC_P_GDMA2 2
#define GDM_OFRC_P_PPE 6
#define GDM_OFRC_P_DROP 7
#define RST_DRX_IDX0 BIT(16)
#define RST_DTX_IDX0 BIT(0)
#define TX_WB_DDONE BIT(6)
#define RX_DMA_BUSY BIT(3)
#define TX_DMA_BUSY BIT(1)
#define RX_DMA_EN BIT(2)
#define TX_DMA_EN BIT(0)
#define GP1_FRC_EN BIT(15)
#define GP1_FC_TX BIT(11)
#define GP1_FC_RX BIT(10)
#define GP1_LNK_DWN BIT(9)
#define GP1_AN_OK BIT(8)
/*
* FE_INT_STATUS
*/
#define CNT_PPE_AF BIT(31)
#define CNT_GDM1_AF BIT(29)
#define PSE_P1_FC BIT(22)
#define PSE_P0_FC BIT(21)
#define PSE_FQ_EMPTY BIT(20)
#define GE1_STA_CHG BIT(18)
#define TX_COHERENT BIT(17)
#define RX_COHERENT BIT(16)
#define TX_DONE_INT1 BIT(9)
#define TX_DONE_INT0 BIT(8)
#define RX_DONE_INT0 BIT(2)
#define TX_DLY_INT BIT(1)
#define RX_DLY_INT BIT(0)
/*
* Ethernet chip registers.RT2880
*/
/* Old FE with New PDMA */
#define PDMA_RELATED 0x0800
/* 1. PDMA */
#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
#define PDMA_RST_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RST_IDX)
#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220) /* FIXME */
#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228) /* FIXME */
#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x280)
#define PDMA_SCH_CFG (PDMA_WRR)
/* TODO: change FE_INT_STATUS->INT_STATUS
* FE_INT_ENABLE->INT_MASK */
#define MDIO_ACCESS RALINK_FRAME_ENGINE_BASE + 0x00
#define MDIO_CFG RALINK_FRAME_ENGINE_BASE + 0x04
#define FE_DMA_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x08
#define FE_RST_GLO RALINK_FRAME_ENGINE_BASE + 0x0C
#define FE_INT_STATUS RALINK_FRAME_ENGINE_BASE + 0x10
#define FE_INT_ENABLE RALINK_FRAME_ENGINE_BASE + 0x14
#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18
#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x1C
#define PAD_RGMII2_MDIO_CFG RALINK_SYSCTL_BASE + 0x58
#define GDMA1_RELATED 0x0500
#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
#define GDMA1_SHRP_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
#define GDMA2_RELATED 0x1500
#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
#define GDMA2_SHRP_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
#define PSE_RELATED 0x0040
#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
#define CDMA_RELATED 0x0080
#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
#define INTERNAL_LOOPBACK_ENABLE 1
#define INTERNAL_LOOPBACK_DISABLE 0
#define TOUT_LOOP 1000
#define ENABLE 1
#define DISABLE 0
VALID_BUFFER_STRUCT rt2880_free_buf_list;
VALID_BUFFER_STRUCT rt2880_busing_buf_list;
static BUFFER_ELEM rt2880_free_buf[PKTBUFSRX];
/*=========================================
PDMA RX Descriptor Format define
=========================================*/
//-------------------------------------------------
typedef struct _PDMA_RXD_INFO1_ PDMA_RXD_INFO1_T;
struct _PDMA_RXD_INFO1_
{
unsigned int PDP0;
};
//-------------------------------------------------
typedef struct _PDMA_RXD_INFO2_ PDMA_RXD_INFO2_T;
struct _PDMA_RXD_INFO2_
{
unsigned int PLEN1 : 14;
unsigned int LS1 : 1;
unsigned int UN_USED : 1;
unsigned int PLEN0 : 14;
unsigned int LS0 : 1;
unsigned int DDONE_bit : 1;
};
//-------------------------------------------------
typedef struct _PDMA_RXD_INFO3_ PDMA_RXD_INFO3_T;
struct _PDMA_RXD_INFO3_
{
unsigned int PDP1;
};
//-------------------------------------------------
typedef struct _PDMA_RXD_INFO4_ PDMA_RXD_INFO4_T;
struct _PDMA_RXD_INFO4_
{
unsigned int FOE_Entry : 14;
unsigned int CRSN : 5;
unsigned int SP : 3;
unsigned int L4F : 1;
unsigned int L4VLD : 1;
unsigned int TACK : 1;
unsigned int IP4F : 1;
unsigned int IP4 : 1;
unsigned int IP6 : 1;
unsigned int UN_USE1 : 4;
};
struct PDMA_rxdesc {
PDMA_RXD_INFO1_T rxd_info1;
PDMA_RXD_INFO2_T rxd_info2;
PDMA_RXD_INFO3_T rxd_info3;
PDMA_RXD_INFO4_T rxd_info4;
};
/*=========================================
PDMA TX Descriptor Format define
=========================================*/
//-------------------------------------------------
typedef struct _PDMA_TXD_INFO1_ PDMA_TXD_INFO1_T;
struct _PDMA_TXD_INFO1_
{
unsigned int SDP0;
};
//-------------------------------------------------
typedef struct _PDMA_TXD_INFO2_ PDMA_TXD_INFO2_T;
struct _PDMA_TXD_INFO2_
{
unsigned int SDL1 : 14;
unsigned int LS1_bit : 1;
unsigned int BURST_bit : 1;
unsigned int SDL0 : 14;
unsigned int LS0_bit : 1;
unsigned int DDONE_bit : 1;
};
//-------------------------------------------------
typedef struct _PDMA_TXD_INFO3_ PDMA_TXD_INFO3_T;
struct _PDMA_TXD_INFO3_
{
unsigned int SDP1;
};
//-------------------------------------------------
typedef struct _PDMA_TXD_INFO4_ PDMA_TXD_INFO4_T;
struct _PDMA_TXD_INFO4_
{
unsigned int VLAN_TAG :16;
unsigned int INS : 1;
unsigned int RESV : 2;
unsigned int UDF : 6;
unsigned int FPORT : 3;
unsigned int TSO : 1;
unsigned int TUI_CO : 3;
};
struct PDMA_txdesc {
PDMA_TXD_INFO1_T txd_info1;
PDMA_TXD_INFO2_T txd_info2;
PDMA_TXD_INFO3_T txd_info3;
PDMA_TXD_INFO4_T txd_info4;
};
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 64
#endif /* CONFIG_SYS_CACHELINE_SIZE */
#define RAETH_NUM_TX_DESC 8
#define RAETH_NUM_RX_DESC 8
static struct PDMA_txdesc tx_ring0_cache[RAETH_NUM_TX_DESC] __attribute__ ((aligned(CONFIG_SYS_CACHELINE_SIZE))); /* TX descriptor ring */
static struct PDMA_rxdesc rx_ring_cache[RAETH_NUM_RX_DESC] __attribute__ ((aligned(CONFIG_SYS_CACHELINE_SIZE))); /* RX descriptor ring */
static int rx_dma_owner_idx0; /* Point to the next RXD DMA wants to use in RXD Ring#0. */
static int rx_wants_alloc_idx0; /* Point to the next RXD CPU wants to allocate to RXD Ring #0. */
static int tx_cpu_owner_idx0; /* Point to the next TXD in TXD_Ring0 CPU wants to use */
static volatile struct PDMA_rxdesc *rx_ring;
static volatile struct PDMA_txdesc *tx_ring0;
static int rx_desc_cnt;
static int rx_desc_threshold;
static char rxRingSize;
static char txRingSize;
static int rt2880_eth_init(struct eth_device* dev, bd_t* bis);
static int rt2880_eth_send(struct eth_device* dev, void *packet, int length);
static int rt2880_eth_recv(struct eth_device* dev);
void rt2880_eth_halt(struct eth_device* dev);
int mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
int mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
static int rt2880_eth_setup(struct eth_device* dev);
static int rt2880_eth_initd;
#define phys_to_bus(a) (a)
volatile uchar *PKT_HEADER_Buf;
static volatile uchar PKT_HEADER_Buf_Pool[(PKTBUFSRX * PKTSIZE_ALIGN) + PKTALIGN];
extern uchar *NetTxPacket; /* THE transmit packet */
volatile uchar RxPktBuf[PKTBUFSRX][1536];
#define PIODIR_R (RALINK_PIO_BASE + 0X24)
#define PIODATA_R (RALINK_PIO_BASE + 0X20)
#define PIODIR3924_R (RALINK_PIO_BASE + 0x4c)
#define PIODATA3924_R (RALINK_PIO_BASE + 0x48)
void START_ETH(struct eth_device *dev ) {
s32 omr;
omr=RALINK_REG(PDMA_GLO_CFG);
udelay(100);
omr |= TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN ;
RALINK_REG(PDMA_GLO_CFG)=omr;
udelay(500);
}
void STOP_ETH(struct eth_device *dev)
{
s32 omr;
omr=RALINK_REG(PDMA_GLO_CFG);
udelay(100);
omr &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN) ;
RALINK_REG(PDMA_GLO_CFG)=omr;
udelay(500);
}
BUFFER_ELEM *rt2880_free_buf_entry_dequeue(VALID_BUFFER_STRUCT *hdr)
{
int zero = 0; /* causes most compilers to place this */
/* value in a register only once */
BUFFER_ELEM *node;
/* Make sure we were not passed a null pointer. */
if (!hdr) {
return (NULL);
}
/* If there is a node in the list we want to remove it. */
if (hdr->head) {
/* Get the node to be removed */
node = hdr->head;
/* Make the hdr point the second node in the list */
hdr->head = node->next;
/* If this is the last node the headers tail pointer needs to be nulled
We do not need to clear the node's next since it is already null */
if (!(hdr->head)) {
hdr->tail = (BUFFER_ELEM *)zero;
}
node->next = (BUFFER_ELEM *)zero;
}
else {
node = NULL;
return (node);
}
/* Restore the previous interrupt lockout level. */
/* Return a pointer to the removed node */
//shnat_validation_flow_table_entry[node->index].state = SHNAT_FLOW_TABLE_NODE_USED;
return (node);
}
static BUFFER_ELEM *rt2880_free_buf_entry_enqueue(VALID_BUFFER_STRUCT *hdr, BUFFER_ELEM *item)
{
int zero =0;
if (!hdr) {
return (NULL);
}
if (item != NULL)
{
/* Temporarily lockout interrupts to protect global buffer variables. */
// Sys_Interrupt_Disable_Save_Flags(&cpsr_flags);
/* Set node's next to point at NULL */
item->next = (BUFFER_ELEM *)zero;
/* If there is currently a node in the linked list, we want to add the
new node to the end. */
if (hdr->head) {
/* Make the last node's next point to the new node. */
hdr->tail->next = item;
/* Make the roots tail point to the new node */
hdr->tail = item;
}
else {
/* If the linked list was empty, we want both the root's head and
tial to point to the new node. */
hdr->head = item;
hdr->tail = item;
}
/* Restore the previous interrupt lockout level. */
}
else
{
printf("\n shnat_flow_table_free_entry_enqueue is called,item== NULL \n");
}
return(item);
} /* MEM_Buffer_Enqueue */
#if defined(CONFIG_PHYLIB)
int rt2880_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
int reg_addr)
{
u32 data;
mii_mgr_read(phy_addr, reg_addr, &data);
return data;
}
int rt2880_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
int reg_addr, u16 data)
{
mii_mgr_write(phy_addr, reg_addr, data);
return 0;
}
phy_interface_t rt2880_phy_interface_get(void)
{
#if defined (GE_MII_FORCE_100) || defined (GE_MII_AN)
return PHY_INTERFACE_MODE_MII;
#elif defined (CONFIG_GE1_SGMII_FORCE_2500)
return PHY_INTERFACE_MODE_SGMII;
#elif defined (GE_RMII_AN)
return PHY_INTERFACE_MODE_RMII;
#elif defined (GE_RGMII_FORCE_1000) || defined (GE_RGMII_AN)
return PHY_INTERFACE_MODE_RGMII;
#else
return PHY_INTERFACE_MODE_MII;
#endif
}
int rt2880_phylib_init(struct eth_device *dev, int phyid)
{
struct mii_dev *bus;
struct phy_device *phydev;
phy_interface_t interface;
int ret;
bus = mdio_alloc();
if (!bus) {
printf("mdio_alloc failed\n");
return -ENOMEM;
}
bus->read = rt2880_phy_read;
bus->write = rt2880_phy_write;
sprintf(bus->name, dev->name);
ret = mdio_register(bus);
if (ret) {
printf("mdio_register failed\n");
free(bus);
return -ENOMEM;
}
interface = rt2880_phy_interface_get();
phydev = phy_connect(bus, phyid, dev, interface);
if (!phydev) {
printf("phy_connect failed\n");
return -ENODEV;
}
phy_config(phydev);
phy_startup(phydev);
return 0;
}
#endif
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
{
u32 read_data;
printf("phy_adr=0x%x, reg_ofs=0x%x\n", phy_adr, reg_ofs);
mii_mgr_read(phy_adr, reg_ofs, &read_data);
*data = read_data;
printf("data = 0x%x\n", *data);
return 0;
}
static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
mii_mgr_write(phy_adr, reg_ofs, data);
return 0;
}
#endif
int rt2880_eth_initialize(bd_t *bis)
{
struct eth_device* dev;
int i;
if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
printf("Failed to allocate memory\n");
return 0;
}
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "mtk_eth");
dev->iobase = RALINK_FRAME_ENGINE_BASE;
dev->init = rt2880_eth_init;
dev->halt = rt2880_eth_halt;
dev->send = rt2880_eth_send;
dev->recv = rt2880_eth_recv;
eth_register(dev);
#if defined(CONFIG_PHYLIB)
rt2880_phylib_init(dev, MAC_TO_GIGAPHY_MODE_ADDR);
#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, mii_reg_read, mii_reg_write);
#endif
rt2880_eth_initd =0;
PKT_HEADER_Buf = PKT_HEADER_Buf_Pool;
NetTxPacket = NULL;
rx_ring = (struct PDMA_rxdesc *)((ulong)&rx_ring_cache[0]);
tx_ring0 = (struct PDMA_txdesc *)((ulong)&tx_ring0_cache[0]);
rt2880_free_buf_list.head = NULL;
rt2880_free_buf_list.tail = NULL;
rt2880_busing_buf_list.head = NULL;
rt2880_busing_buf_list.tail = NULL;
//2880_free_buf
/*
* Setup packet buffers, aligned correctly.
*/
rt2880_free_buf[0].pbuf = (unsigned char *)&RxPktBuf[0];
rt2880_free_buf[0].pbuf += PKTALIGN - 1;
rt2880_free_buf[0].pbuf -= (ulong)rt2880_free_buf[0].pbuf % PKTALIGN;
rt2880_free_buf[0].next = NULL;
rt2880_free_buf_entry_enqueue(&rt2880_free_buf_list,&rt2880_free_buf[0]);
#ifdef DEBUG
printf("\n rt2880_free_buf[0].pbuf = 0x%08X \n",rt2880_free_buf[0].pbuf);
#endif
for (i = 1; i < PKTBUFSRX; i++) {
rt2880_free_buf[i].pbuf = rt2880_free_buf[0].pbuf + (i)*PKTSIZE_ALIGN;
rt2880_free_buf[i].next = NULL;
#ifdef DEBUG
printf("\n rt2880_free_buf[%d].pbuf = 0x%08X\n",i,rt2880_free_buf[i].pbuf);
#endif
rt2880_free_buf_entry_enqueue(&rt2880_free_buf_list,&rt2880_free_buf[i]);
}
for (i = 0; i < PKTBUFSRX; i++)
{
rt2880_free_buf[i].tx_idx = RAETH_NUM_TX_DESC;
#ifdef DEBUG
printf("\n rt2880_free_buf[%d] = 0x%08X,rt2880_free_buf[%d].next=0x%08X \n",i,&rt2880_free_buf[i],i,rt2880_free_buf[i].next);
#endif
}
return 1;
}
#if defined(MT7623_ASIC_BOARD)
void mt7623_ethifsys_init(void)
{
#define TRGPLL_CON0 (0x10209280)
#define TRGPLL_CON1 (0x10209284)
#define TRGPLL_CON2 (0x10209288)
#define TRGPLL_PWR_CON0 (0x1020928C)
#define ETHPLL_CON0 (0x10209290)
#define ETHPLL_CON1 (0x10209294)
#define ETHPLL_CON2 (0x10209298)
#define ETHPLL_PWR_CON0 (0x1020929C)
#define ETH_PWR_CON (0x100062A0)
#define HIF_PWR_CON (0x100062A4)
printf("Enter mt7623_ethifsys_init()\n");
//=========================================================================
// Enable ETHPLL & TRGPLL
//=========================================================================
// xPLL PWR ON
u32 temp, pwr_ack_status;
temp = RALINK_REG(ETHPLL_PWR_CON0);
RALINK_REG(ETHPLL_PWR_CON0) = temp | 0x1;
temp = RALINK_REG(TRGPLL_PWR_CON0);
RALINK_REG(TRGPLL_PWR_CON0) = temp | 0x1;
udelay(5); // wait for xPLL_PWR_ON ready (min delay is 1us)
// xPLL ISO Disable
temp = RALINK_REG(ETHPLL_PWR_CON0);
RALINK_REG(ETHPLL_PWR_CON0) = temp & ~0x2;
temp = RALINK_REG(TRGPLL_PWR_CON0);
RALINK_REG(TRGPLL_PWR_CON0) = temp & ~0x2;
// xPLL Frequency Set
temp = RALINK_REG(ETHPLL_CON0);
RALINK_REG(ETHPLL_CON0) = temp | 0x1;
#if defined (CONFIG_GE1_TRGMII_FORCE_2900)
temp = RALINK_REG(TRGPLL_CON0);
RALINK_REG(TRGPLL_CON0) = temp | 0x1;
#elif defined (CONFIG_GE1_TRGMII_FORCE_2600)
RALINK_REG(TRGPLL_CON1) = 0xB2000000;
temp = RALINK_REG(TRGPLL_CON0);
RALINK_REG(TRGPLL_CON0) = temp | 0x1;
#elif defined (CONFIG_GE1_TRGMII_FORCE_2000)
RALINK_REG(TRGPLL_CON1) = 0xCCEC4EC5;
RALINK_REG(TRGPLL_CON0) = 0x121;
#else
temp = RALINK_REG(TRGPLL_CON0);
RALINK_REG(TRGPLL_CON0) = temp | 0x1;
#endif
udelay(40); // wait for PLL stable (min delay is 20us)
//=========================================================================
// Power on ETHDMASYS and HIFSYS
//=========================================================================
// Power on ETHDMASYS
RALINK_REG(0x10006000) = 0x0b160001;
pwr_ack_status = (RALINK_REG(ETH_PWR_CON) & 0x0000f000) >> 12;
if(pwr_ack_status == 0x0) {
printf("ETH already turn on and power on flow will be skipped\n");
} else {
temp = RALINK_REG(ETH_PWR_CON);
RALINK_REG(ETH_PWR_CON) = temp | 0x4; // PWR_ON
temp = RALINK_REG(ETH_PWR_CON);
RALINK_REG(ETH_PWR_CON) = temp | 0x8; // PWR_ON_S
udelay(5); // wait power settle time (min delay is 1us)
temp = RALINK_REG(ETH_PWR_CON);
RALINK_REG(ETH_PWR_CON) = temp & ~0x10; // PWR_CLK_DIS
temp = RALINK_REG(ETH_PWR_CON);
RALINK_REG(ETH_PWR_CON) = temp & ~0x2; // PWR_ISO
temp = RALINK_REG(ETH_PWR_CON);
RALINK_REG(ETH_PWR_CON) = temp & ~0x100; // SRAM_PDN 0
temp = RALINK_REG(ETH_PWR_CON);
RALINK_REG(ETH_PWR_CON) = temp & ~0x200; // SRAM_PDN 1
temp = RALINK_REG(ETH_PWR_CON);
RALINK_REG(ETH_PWR_CON) = temp & ~0x400; // SRAM_PDN 2
temp = RALINK_REG(ETH_PWR_CON);
RALINK_REG(ETH_PWR_CON) = temp & ~0x800; // SRAM_PDN 3
udelay(5); // wait SRAM settle time (min delay is 1Us)
temp = RALINK_REG(ETH_PWR_CON);
RALINK_REG(ETH_PWR_CON) = temp | 0x1; // PWR_RST_B
}
// Power on HIFSYS
pwr_ack_status = (RALINK_REG(HIF_PWR_CON) & 0x0000f000) >> 12;
if(pwr_ack_status == 0x0) {
printf("HIF already turn on and power on flow will be skipped\n");
} else {
temp = RALINK_REG(HIF_PWR_CON);
RALINK_REG(HIF_PWR_CON) = temp | 0x4; // PWR_ON
temp = RALINK_REG(HIF_PWR_CON);
RALINK_REG(HIF_PWR_CON) = temp | 0x8; // PWR_ON_S
udelay(5); // wait power settle time (min delay is 1us)
temp = RALINK_REG(HIF_PWR_CON);
RALINK_REG(HIF_PWR_CON) = temp & ~0x10; // PWR_CLK_DIS
temp = RALINK_REG(HIF_PWR_CON);
RALINK_REG(HIF_PWR_CON) = temp & ~0x2; // PWR_ISO
temp = RALINK_REG(HIF_PWR_CON);
RALINK_REG(HIF_PWR_CON) = temp & ~0x100; // SRAM_PDN 0
temp = RALINK_REG(HIF_PWR_CON);
RALINK_REG(HIF_PWR_CON) = temp & ~0x200; // SRAM_PDN 1
temp = RALINK_REG(HIF_PWR_CON);
RALINK_REG(HIF_PWR_CON) = temp & ~0x400; // SRAM_PDN 2
temp = RALINK_REG(HIF_PWR_CON);
RALINK_REG(HIF_PWR_CON) = temp & ~0x800; // SRAM_PDN 3
udelay(5); // wait SRAM settle time (min delay is 1Us)
temp = RALINK_REG(HIF_PWR_CON);
RALINK_REG(HIF_PWR_CON) = temp | 0x1; // PWR_RST_B
}
/* Release mt7530 reset */
temp = le32_to_cpu(*(volatile u_long *)(0x1b000034));
temp &= ~(BIT(2));
*(volatile u_long *)(0x1b000034) = temp;
}
void mt7623_pinmux_set(void)
{
u32 regValue;
printf("[mt7623_pinmux_set]start\n");
/* Pin277: ESW_RST (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ad0));
regValue &= ~(BITS(6,8));
regValue |= BIT(6);
*(volatile u_long *)(0x10005ad0) = regValue;
/* Pin262: G2_TXEN (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005aa0));
regValue &= ~(BITS(6,8));
regValue |= BIT(6);
*(volatile u_long *)(0x10005aa0) = regValue;
/* Pin263: G2_TXD3 (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005aa0));
regValue &= ~(BITS(9,11));
regValue |= BIT(9);
*(volatile u_long *)(0x10005aa0) = regValue;
/* Pin264: G2_TXD2 (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005aa0));
regValue &= ~(BITS(12,14));
regValue |= BIT(12);
*(volatile u_long *)(0x10005aa0) = regValue;
/* Pin265: G2_TXD1 (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ab0));
regValue &= ~(BITS(0,2));
regValue |= BIT(0);
*(volatile u_long *)(0x10005ab0) = regValue;
/* Pin266: G2_TXD0 (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ab0));
regValue &= ~(BITS(3,5));
regValue |= BIT(3);
*(volatile u_long *)(0x10005ab0) = regValue;
/* Pin267: G2_TXC (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ab0));
regValue &= ~(BITS(6,8));
regValue |= BIT(6);
*(volatile u_long *)(0x10005ab0) = regValue;
/* Pin268: G2_RXC (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ab0));
regValue &= ~(BITS(9,11));
regValue |= BIT(9);
*(volatile u_long *)(0x10005ab0) = regValue;
/* Pin269: G2_RXD0 (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ab0));
regValue &= ~(BITS(12,14));
regValue |= BIT(12);
*(volatile u_long *)(0x10005ab0) = regValue;
/* Pin270: G2_RXD1 (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ac0));
regValue &= ~(BITS(0,2));
regValue |= BIT(0);
*(volatile u_long *)(0x10005ac0) = regValue;
/* Pin271: G2_RXD2 (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ac0));
regValue &= ~(BITS(3,5));
regValue |= BIT(3);
*(volatile u_long *)(0x10005ac0) = regValue;
/* Pin272: G2_RXD3 (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ac0));
regValue &= ~(BITS(6,8));
regValue |= BIT(6);
*(volatile u_long *)(0x10005ac0) = regValue;
/* Pin274: G2_RXDV (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ac0));
regValue &= ~(BITS(12,14));
regValue |= BIT(12);
*(volatile u_long *)(0x10005ac0) = regValue;
/* Pin275: MDC (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ad0));
regValue &= ~(BITS(0,2));
regValue |= BIT(0);
*(volatile u_long *)(0x10005ad0) = regValue;
/* Pin276: MDIO (1) */
regValue = le32_to_cpu(*(volatile u_long *)(0x10005ad0));
regValue &= ~(BITS(3,5));
regValue |= BIT(3);
*(volatile u_long *)(0x10005ad0) = regValue;
printf("[mt7623_pinmux_set]end\n");
}
void wait_loop(void) {
int i,j;
int read_data;
j =0;
while (j< 10) {
for(i = 0; i<32; i = i+1){
read_data = *(volatile u_long *)(0x1B110610);
*(volatile u_long *)(0x1B110610) = read_data;
}
j++;
}
}
void trgmii_calibration_7623(void) {
unsigned int tap_a[5] = {0, 0, 0, 0, 0}; // minumum delay for all correct
unsigned int tap_b[5] = {0, 0, 0, 0, 0}; // maximum delay for all correct
unsigned int final_tap[5];
unsigned int rxc_step_size;
unsigned int rxd_step_size;
unsigned int read_data;
unsigned int tmp;
unsigned int rd_wd;
int i;
unsigned int err_cnt[5];
unsigned int init_toggle_data;
unsigned int err_flag[5];
unsigned int err_total_flag;
unsigned int training_word;
unsigned int rd_tap;
unsigned int is_mt7623_e1 = 0;
u32 TRGMII_7623_base;
u32 TRGMII_7623_RD_0;
u32 TRGMII_RCK_CTRL;
TRGMII_7623_base = ETHDMASYS_ETH_SW_BASE+0x0300;
TRGMII_7623_RD_0 = TRGMII_7623_base + 0x10;
TRGMII_RCK_CTRL = TRGMII_7623_base;
rxd_step_size =0x1;
rxc_step_size =0x4;
init_toggle_data = 0x00000055;
training_word = 0x000000AC;
//printk("Calibration begin ........");
*(volatile u_long *)(TRGMII_7623_base +0x04) &= 0x3fffffff; // RX clock gating in MT7623
*(volatile u_long *)(TRGMII_7623_base +0x00) |= 0x80000000; // Assert RX reset in MT7623
*(volatile u_long *)(TRGMII_7623_base +0x78) |= 0x00002000; // Set TX OE edge in MT7623
*(volatile u_long *)(TRGMII_7623_base +0x04) |= 0xC0000000; // Disable RX clock gating in MT7623
*(volatile u_long *)(TRGMII_7623_base ) &= 0x7fffffff; // Release RX reset in MT7623
//printk("Check Point 1 .....\n");
for (i = 0 ; i<5 ; i++) {
*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) |= 0x80000000; // Set bslip_en = 1
}
//printk("Enable Training Mode in MT7530\n");
mii_mgr_read(0x1F,0x7A40,&read_data);
read_data |= 0xc0000000;
mii_mgr_write(0x1F,0x7A40,read_data); //Enable Training Mode in MT7530
err_total_flag = 0;
//printk("Adjust RXC delay in MT7623\n");
read_data =0x0;
while (err_total_flag == 0 && read_data != 0x68) {
//printk("2nd Enable EDGE CHK in MT7623\n");
/* Enable EDGE CHK in MT7623*/
for (i = 0 ; i<5 ; i++) {
tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
tmp |= 0x40000000;
*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
}
wait_loop();
err_total_flag = 1;
for (i = 0 ; i<5 ; i++) {
err_cnt[i] = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 8) & 0x0000000f;
rd_wd = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 16) & 0x000000ff;
//printk("ERR_CNT = %d, RD_WD =%x\n",err_cnt[i],rd_wd);
if ( err_cnt[i] !=0 ) {
err_flag[i] = 1;
}
else if (rd_wd != 0x55) {
err_flag[i] = 1;
}
else {
err_flag[i] = 0;
}
err_total_flag = err_flag[i] & err_total_flag;
}
//printk("2nd Disable EDGE CHK in MT7623\n");
/* Disable EDGE CHK in MT7623*/
for (i = 0 ; i<5 ; i++) {
tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
tmp |= 0x40000000;
*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
}
wait_loop();
/* Adjust RXC delay */
if(is_mt7623_e1)
*(volatile u_long *)(TRGMII_7623_base +0x00) |= 0x80000000; // Assert RX reset in MT7623
*(volatile u_long *)(TRGMII_7623_base +0x04) &= 0x3fffffff; // RX clock gating in MT7623
read_data = *(volatile u_long *)(TRGMII_7623_base);
if (err_total_flag == 0) {
tmp = (read_data & 0x0000007f) + rxc_step_size;
//printk(" RXC delay = %d\n", tmp);
read_data >>= 8;
read_data &= 0xffffff80;
read_data |= tmp;
read_data <<=8;
read_data &= 0xffffff80;
read_data |=tmp;
*(volatile u_long *)(TRGMII_7623_base) = read_data;
} else {
tmp = (read_data & 0x0000007f) + 16;
//printk(" RXC delay = %d\n", tmp);
read_data >>= 8;
read_data &= 0xffffff80;
read_data |= tmp;
read_data <<=8;
read_data &= 0xffffff80;
read_data |=tmp;
*(volatile u_long *)(TRGMII_7623_base) = read_data;
}
read_data &=0x000000ff;
if(is_mt7623_e1)
*(volatile u_long *)(TRGMII_7623_base ) &= 0x7fffffff; // Release RX reset in MT7623
*(volatile u_long *)(TRGMII_7623_base +0x04) |= 0xC0000000; // Disable RX clock gating in MT7623
for (i = 0 ; i<5 ; i++) {
*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = (*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) | 0x80000000; // Set bslip_en = ~bit_slip_en
}
}
//printk("Finish RXC Adjustment while loop\n");
//printk("Read RD_WD MT7623\n");
/* Read RD_WD MT7623*/
for (i = 0 ; i<5 ; i++) {
rd_tap = 0;
while (err_flag[i] != 0 && rd_tap != 128) {
/* Enable EDGE CHK in MT7623*/
tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
tmp |= 0x40000000;
*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
wait_loop();
read_data = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
err_cnt[i] = (read_data >> 8) & 0x0000000f; // Read MT7623 Errcnt
rd_wd = (read_data >> 16) & 0x000000ff;
if (err_cnt[i] != 0 || rd_wd !=0x55){
err_flag [i] = 1;
}
else {
err_flag[i] =0;
}
/* Disable EDGE CHK in MT7623*/
*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) &= 0x4fffffff;
tmp |= 0x40000000;
*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
wait_loop();
//err_cnt[i] = ((read_data) >> 8) & 0x0000000f; // Read MT7623 Errcnt
if (err_flag[i] !=0) {
rd_tap = (read_data & 0x0000007f) + rxd_step_size; // Add RXD delay in MT7623
read_data = (read_data & 0xffffff80) | rd_tap;
*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data;
tap_a[i] = rd_tap;
} else {
rd_tap = (read_data & 0x0000007f) + 48;
read_data = (read_data & 0xffffff80) | rd_tap;
*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data;
}