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SPMDParallelizer.cpp
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SPMDParallelizer.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2022 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at https://www.eclipse.org/legal/epl-2.0/
* or the Apache License, Version 2.0 which accompanies this distribution and
* is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following
* Secondary Licenses when the conditions for such availability set
* forth in the Eclipse Public License, v. 2.0 are satisfied: GNU
* General Public License, version 2 with the GNU Classpath
* Exception [1] and GNU General Public License, version 2 with the
* OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include "optimizer/SPMDParallelizer.hpp"
#include <limits.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "compile/Compilation.hpp"
#include "compile/Method.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "cs2/allocator.h"
#include "cs2/arrayof.h"
#include "cs2/bitvectr.h"
#include "cs2/sparsrbit.h"
#include "env/StackMemoryRegion.hpp"
#include "env/TRMemory.hpp"
#include "env/VerboseLog.hpp"
#include "il/AliasSetInterface.hpp"
#include "il/AutomaticSymbol.hpp"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/BitVector.hpp"
#include "infra/Cfg.hpp"
#include "infra/HashTab.hpp"
#include "infra/List.hpp"
#include "infra/TRCfgEdge.hpp"
#include "infra/TRCfgNode.hpp"
#include "optimizer/Dominators.hpp"
#include "optimizer/InductionVariable.hpp"
#include "optimizer/LoopCanonicalizer.hpp"
#include "optimizer/Optimization_inlines.hpp"
#include "optimizer/Optimizations.hpp"
#include "optimizer/Optimizer.hpp"
#include "optimizer/SPMDPreCheck.hpp"
#include "optimizer/Structure.hpp"
#include "optimizer/TransformUtil.hpp"
#include "optimizer/UseDefInfo.hpp"
#include "optimizer/ValueNumberInfo.hpp"
#include "runtime/J9Runtime.hpp"
#include "ras/DebugCounter.hpp"
#include "env/annotations/GPUAnnotation.hpp"
#define OPT_SIMD_DETAILS "O^O AUTO SIMD: "
#define INVALID_STRIDE INT_MAX
#define VECTOR_SIZE 16
#define VECTOR_LENGTH TR::VectorLength128
#define INVALID_ADDR (TR::Node *)-1
namespace TR { class OptimizationManager; }
namespace TR { class ParameterSymbol; }
typedef TR::CodeGenerator::gpuMapElement gpuMapElement;
// SIMD_TODO: use visitCount or some caching?
static bool hasPIV(TR::Node *node, TR::SymbolReference *piv)
{
if (node->getOpCodeValue() == TR::iload &&
node->getSymbolReference() == piv)
return true;
for (int32_t i = 0; i < node->getNumChildren(); i++)
{
if (hasPIV(node->getChild(i), piv))
return true;
}
return false;
}
int32_t TR_SPMDKernelParallelizer::getUnrollCount(TR::DataType dt)
{
int32_t unrollCount = -1;
switch(dt)
{
case TR::Int8:
unrollCount=VECTOR_SIZE; break;
case TR::Int16:
unrollCount=VECTOR_SIZE/2; break;
case TR::Int32:
case TR::Float:
unrollCount=VECTOR_SIZE/4; break;
case TR::Int64:
case TR::Double:
unrollCount=VECTOR_SIZE/8; break;
}
return unrollCount;
}
TR::Node * TR_SPMDKernelParallelizer::findLoopDataType(TR::Node* node, TR::Compilation *comp)
{
if(!node)
return node;
if (_visitedNodes.isSet(node->getGlobalIndex()))
return NULL;
_visitedNodes.set(node->getGlobalIndex());
if(node->getOpCode().hasSymbolReference() && node->getSymbolReference()->getSymbol()->isArrayShadowSymbol())
return node;
for(int32_t i=0;i<node->getNumChildren();i++)
{
if(findLoopDataType(node->getChild(i),comp))
return node;
}
return NULL;
}
void TR_SPMDKernelParallelizer::setLoopDataType(TR_RegionStructure *loop,TR::Compilation *comp)
{
TR_ScratchList<TR::Block> blocksInLoop(trMemory());
loop->getBlocks(&blocksInLoop);
ListIterator<TR::Block> blocksIt(&blocksInLoop);
//clear the node visit list as we need to visit again.
_visitedNodes.empty();
for (TR::Block *nextBlock = blocksIt.getCurrent(); nextBlock; nextBlock=blocksIt.getNext())
{
for (TR::TreeTop *tt = nextBlock->getEntry() ; tt != nextBlock->getExit() ; tt = tt->getNextTreeTop())
{
TR::Node *node = findLoopDataType(tt->getNode(),comp);
if(node)
{
TR_HashId id = 0;
_loopDataType->add(loop,id,node->duplicateTree());
return;
}
}
}
}
// SIMD_TODO: use visitCount or some caching?
bool TR_SPMDKernelParallelizer::isAffineAccess(TR::Compilation *comp, TR::Node *node, TR_RegionStructure *loop, TR::SymbolReference *piv, int32_t &pivStride)
{
int32_t child1Stride = INVALID_STRIDE;
int32_t child2Stride = INVALID_STRIDE;
pivStride = 0;
if (node->getOpCodeValue() == TR::i2l)
{
if (isAffineAccess(comp, node->getFirstChild(), loop, piv, child1Stride))
{
pivStride = child1Stride;
return true;
}
}
else if (node->getOpCode().isAdd() || node->getOpCode().isSub())
{
if (isAffineAccess(comp, node->getFirstChild(), loop, piv, child1Stride) &&
isAffineAccess(comp, node->getSecondChild(), loop, piv, child2Stride))
{
if (child1Stride != INVALID_STRIDE && child2Stride != INVALID_STRIDE)
pivStride = node->getOpCode().isAdd() ? child1Stride + child2Stride : child1Stride - child2Stride;
else
{
pivStride = INVALID_STRIDE;
}
return true;
}
}
else if (node->getOpCode().isMul())
{
bool isSecondChildInvar = loop->isExprInvariant(node->getSecondChild());
bool isFirstChildInvar = loop->isExprInvariant(node->getFirstChild());
if (isFirstChildInvar && isSecondChildInvar)
{
return true;
}
else if (isSecondChildInvar)
{
if (isAffineAccess(comp, node->getFirstChild(), loop, piv, child1Stride))
{
if (child1Stride == 0)
return true;
else if (child1Stride != INVALID_STRIDE &&
node->getSecondChild()->getOpCode().isLoadConst())
pivStride = node->getSecondChild()->get64bitIntegralValue() * child1Stride;
else
{
pivStride = INVALID_STRIDE;
}
return true;
}
}
else if (isFirstChildInvar)
{
if (isAffineAccess(comp, node->getSecondChild(), loop, piv, child2Stride))
{
if (child2Stride == 0)
return true;
else if (child2Stride != INVALID_STRIDE &&
node->getFirstChild()->getOpCode().isLoadConst())
pivStride = node->getFirstChild()->get64bitIntegralValue() * child2Stride;
else
{
pivStride = INVALID_STRIDE;
}
return true;
}
}
}
else if (loop->isExprInvariant(node))
{
return true;
}
else if(node->getOpCodeValue() == TR::iload)
{
if (node->getSymbolReference() == piv)
{
pivStride = 1;
return true;
}
for (int32_t idx = 0; idx < _pivList.NumberOfElements(); idx++) // SIMD_TODO: faster way ?
{
if (node->getSymbolReference() == _pivList[idx]->getSymRef())
{
return true;
}
}
}
return false;
}
void TR_SPMDKernelParallelizer::genVectorAccessForScalar(TR::Node *parent, int32_t childIndex, TR::Node *node)
{
//we need to duplicate tree because this node could be commoned with any other expression inside the loop, e.g. address expression. we don't want to vectorize all the common-ed nodes
TR::Node *splatsNode = TR::Node::create(TR::vsplats, 1, node->duplicateTree());
node->recursivelyDecReferenceCount();
// can visit the commoned node again, if needed.
_visitedNodes.reset(node->getGlobalIndex());
parent->setAndIncChild(childIndex, splatsNode);
}
static void collectUses(TR::Node *defNode, TR::Compilation *comp, TR_UseDefInfo *info, CS2::ArrayOf<TR::Node *, TR::Allocator> &useNodesOfDefsInLoop)
{
int32_t useDefIndex = defNode->getUseDefIndex();
TR_UseDefInfo::BitVector usesOfThisDef(comp->allocator());
info->getUsesFromDef(usesOfThisDef, useDefIndex);
if (usesOfThisDef.IsZero())
return;
TR_UseDefInfo::BitVector::Cursor cursor(usesOfThisDef);
for (cursor.SetToFirstOne(); cursor.Valid(); cursor.SetToNextOne())
{
int32_t useIndex = (int32_t) cursor + info->getFirstUseIndex();
useNodesOfDefsInLoop[useNodesOfDefsInLoop.NumberOfElements()]=info->getNode(useIndex);
}
}
bool TR_SPMDKernelParallelizer::visitTreeTopToSIMDize(TR::TreeTop *tt, TR_SPMDKernelInfo *pSPMDInfo, bool isCheckMode, TR_RegionStructure *loop, CS2::ArrayOf<TR::Node *, TR::Allocator> &useNodesOfDefsInLoop, TR::Compilation *comp, TR_UseDefInfo *useDefInfo, SharedSparseBitVector &defsInLoop, SharedSparseBitVector* usesInLoop, TR_HashTab* reductionHashTab)
{
TR::Node *node = tt->getNode();
TR::ILOpCode scalarOp = node->getOpCode();
TR::SymbolReference *piv = pSPMDInfo->getInductionVariableSymRef();
bool trace = comp->trace(OMR::SPMDKernelParallelization);
// SIMD_TODO: check first child if node is TR::TreeTop
if (trace)
{
traceMsg(comp," Visiting Tree Top [%p] during %s mode \n", node, isCheckMode ? "detection" : "transformation");
}
if (scalarOp.isStore())
{
TR_HashId id = 0;
if (scalarOp.isIndirect())
{
if (!_loopDataType->locate(loop,id))
{
_loopDataType->add(loop,id,node->duplicateTree());
_loopDataType->locate(loop,id); //add can invalidate hashId so locate is rerun to refresh the hashId
}
if (((TR::Node *)_loopDataType->getData(id))->getSize() != node->getSize() && isCheckMode)
{
if (trace) traceMsg(comp," Node size does not match loop data type for node: %p\n", node);
return false;
}
TR::SymbolReference *symRef = node->getSymbolReference();
TR::SymbolReference *vecSymRef = pSPMDInfo->getVectorSymRef(symRef);
TR::ILOpCode scalarOp = node->getOpCode();
TR::ILOpCodes vectorOpCode = TR::ILOpCode::convertScalarToVector(scalarOp.getOpCodeValue());
if (isCheckMode && vectorOpCode == TR::BadILOp)
return false;
TR_ASSERT(vectorOpCode != TR::BadILOp, "BAD IL Opcode to be assigned during transformation");
if (isCheckMode && !comp->cg()->getSupportsOpCodeForAutoSIMD(vectorOpCode, node->getDataType(), VECTOR_LENGTH))
return false;
if (!isCheckMode)
{
// just convert the original scalar store into vector store
TR::Node::recreate(node, vectorOpCode);
// TODO: use best vector length available
vecSymRef = comp->getSymRefTab()->findOrCreateArrayShadowSymbolRef(node->getDataType().scalarToVector(TR::VectorLength128), NULL);
node->setSymbolReference(vecSymRef);
}
else if (loop->isExprInvariant(node->getFirstChild()))
{
if (trace)
traceMsg(comp, " node %p has loop invariant address\n", node);
return false;
}
else
{
int32_t pivStride = INVALID_STRIDE;
bool affine = isAffineAccess(comp, node->getFirstChild(), loop, piv, pivStride);
if (trace)
traceMsg(comp, " node %p affine = %d stride = %d\n", node, affine, pivStride);
if (!affine || !(pivStride*getUnrollCount(node->getDataType()) == VECTOR_SIZE))
return false;
}
return visitNodeToSIMDize(node, 1, node->getSecondChild(), pSPMDInfo, isCheckMode, loop, comp, usesInLoop, useNodesOfDefsInLoop, useDefInfo, defsInLoop, reductionHashTab, /*storeSymRef*/0);
}
else
{
// Direct store
if (node->getOpCodeValue() == TR::istore )
{
//check if it's one of the induction variables
bool isPIVDefNode = false;
for (int32_t iv=0; iv < _pivList.NumberOfElements(); iv++)
{
if (node->getSymbolReference() == _pivList[iv]->getSymRef())
{
isPIVDefNode=true;
break;
}
}
if (isPIVDefNode)
{
int32_t pivStride = INVALID_STRIDE;
bool isAffine = isAffineAccess(comp, node->getFirstChild(), loop, piv, pivStride);
// if the induction variable is not incremented after the soon to be vectorized instructions, then we bail out (see: openj9/issues/9331)
if (isCheckMode)
{
if (!(tt->getNextTreeTop()->getNode()->getOpCode().isBooleanCompare() &&
tt->getNextTreeTop()->getNode()->getOpCode().isBranch() &&
hasPIV(tt->getNextTreeTop()->getNode(), piv)) ||
tt->getNextTreeTop()->getNextTreeTop()->getNode()->getOpCodeValue() != TR::BBEnd)
{
traceMsg(comp, " Induction variable may be incremented before vectorized operations, "
"this may cause functionally incorrect result. Vectorization not performed. see: openj9/issues/9331.\n");
return false;
}
}
// if this is transformation mode and this PIV is used by a vectorized expression and satisfies
// affine access conditions, duplicate the trees to create a vectorized loop increment
// for the vectorized version of the PIV
if (!isCheckMode && pSPMDInfo->getIsPIVVectorized() && isAffine)
{
// adding increments for vectorized induction variables at the same location
// where the scalar induction variable is incremented
TR::TreeTop *currTree=tt;
TR::TreeTop *prevTree=tt->getPrevTreeTop();
TR::Node * dupNode = node->duplicateTree();
TR::TreeTop* dupTree = TR::TreeTop::create(comp, dupNode, NULL, NULL);
prevTree->join(dupTree);
dupTree->join(currTree);
TR::SymbolReference *symRef = node->getSymbolReference();
TR::SymbolReference *vecSymRef = pSPMDInfo->getVectorSymRef(symRef);
if (vecSymRef == NULL)
{
vecSymRef = comp->cg()->allocateLocalTemp(node->getDataType().scalarToVector(TR::VectorLength128)); // need to handle alignment?
pSPMDInfo->addVectorSymRef(symRef, vecSymRef);
if (trace)
traceMsg(comp, " created new symRef #%d for #%d\n", vecSymRef->getReferenceNumber(), symRef->getReferenceNumber());
}
TR::ILOpCode scalarOp = node->getOpCode();
TR::ILOpCodes vectorOpCode = TR::ILOpCode::convertScalarToVector(scalarOp.getOpCodeValue());
TR_ASSERT(vectorOpCode != TR::BadILOp, "BAD IL Opcode to be assigned during transformation");
dupNode->setSymbolReference(vecSymRef);
TR::Node::recreate(dupNode, vectorOpCode);
if (trace)
traceMsg(comp, " Duplicating trees [%p] into [%p] and vectorizing for Vectorized PIV increment\n", node, dupNode);
return visitNodeToSIMDize(dupNode, 0, dupNode->getFirstChild(), pSPMDInfo, false, loop, comp, usesInLoop, useNodesOfDefsInLoop, useDefInfo, defsInLoop, reductionHashTab, /*storeSymRef*/0);
}
// this is an increment step of the PIV, don't vectorize it
return isAffine;
}
}
if (isCheckMode)
{
TR_SPMDReductionInfo* reductionInfo;
if (reductionHashTab->locate(node->getSymbolReference(), id))
{
reductionInfo = (TR_SPMDReductionInfo*)reductionHashTab->getData(id);
if (trace) traceMsg(comp, " visitTreeTopToSIMDize: Found reductionInfo for node: %p, symRef: %p\n", node, node->getSymbolReference());
}
else
{
reductionInfo = new (comp->trStackMemory()) TR_SPMDReductionInfo(comp);
reductionInfo->reductionOp = Reduction_OpUninitialized;
reductionInfo->reductionSymRef = node->getSymbolReference();
reductionHashTab->add(node->getSymbolReference(), id, reductionInfo);
if (trace) traceMsg(comp, " visitTreeTopToSIMDize: Created reductionInfo for node: %p, symRef: %p\n", node, node->getSymbolReference());
}
//if autoSIMD reduction is not supported, immediately set the reduction to invalid.
if (!autoSIMDReductionSupported(comp, node))
reductionInfo->reductionOp = Reduction_Invalid;
//Similar to the piv, nodes that store to a reduction symref are not added to defsInLoop.
//However, we do not know which symrefs are reduction symrefs at this time.
//As a result we keep track of potential stores to reduction symrefs.
//If we find out that it is not a supported reduction symref, the node is added to defsInLoop
//If the reductionOp field is Reduction_Invalid we already know it is not a valid or supported reduction
if (reductionInfo->reductionOp != Reduction_Invalid)
{
//isReduction is run to check that the reduction matches the reduction pattern
//-only uses the reduction symref once
//-reduction operation is supported (currently only add and mul)
//-only the reduction operation is used between the store node and the reduction variable load
if (isReduction(comp, loop, node->getFirstChild(), reductionInfo, reductionInfo->reductionOp))
{
if (trace) traceMsg(comp, " visitTreeTopToSIMDize: Reduction pattern match on node: %p\n", node);
//add node to list of nodes that might be a store to a reduction variable
reductionInfo->storeNodes.add(node);
}
else
{
//we know this isn't a supported reduction at this point
if (trace) traceMsg(comp, " visitTreeTopToSIMDize: Reduction pattern mismatch for node: %p\n", node);
reductionInfo->reductionOp = Reduction_Invalid;
defsInLoop[node->getGlobalIndex()] = true;
collectUses(node, comp, useDefInfo, useNodesOfDefsInLoop);
//the symref is not a reduction variable or not a supported reduction variable
//as a result the nodes that store to it are no longer considered stores to a reduction variable
//this adds the recorded nodes back into defsInLoop
ListIterator<TR::Node> nodeIt(&reductionInfo->storeNodes);
for (TR::Node *nextNode = nodeIt.getCurrent(); nextNode; nextNode=nodeIt.getNext())
{
if (trace) traceMsg(comp, " visitTreeTopToSIMDize: Adding recorded invalid reduction node to defsInLoop. node: %p\n", nextNode);
defsInLoop[nextNode->getGlobalIndex()] = true;
collectUses(nextNode, comp, useDefInfo, useNodesOfDefsInLoop);
}
}
}
else
{
//non-reductions are just added to defsInLoop
defsInLoop[node->getGlobalIndex()] = true;
collectUses(node, comp, useDefInfo, useNodesOfDefsInLoop);
}
}
TR::ILOpCode scalarOp = node->getOpCode();
TR::ILOpCodes vectorOpCode = TR::ILOpCode::convertScalarToVector(scalarOp.getOpCodeValue());
if (isCheckMode && vectorOpCode == TR::BadILOp)
return false;
if (loop->isExprInvariant(node->getFirstChild()))
{
if (isCheckMode)
return true;
if (!isCheckMode)
{
TR::TreeTop *currTree=tt;
TR::TreeTop *prevTree=tt->getPrevTreeTop();
TR::Node * dupNode = node->duplicateTree();
TR::TreeTop* dupTree = TR::TreeTop::create(comp, dupNode, NULL, NULL);
prevTree->join(dupTree);
dupTree->join(currTree);
}
}
if (!_loopDataType->locate(loop,id))
{
_loopDataType->add(loop,id,node->duplicateTree());
_loopDataType->locate(loop,id); //add can invalidate hashId so locate is rerun to refresh the hashId
}
if (((TR::Node *)_loopDataType->getData(id))->getSize() != node->getSize() && isCheckMode)
{
if (trace) traceMsg(comp," Node size does not match loop data type for node: %p\n", node);
return false;
}
TR::SymbolReference *symRef = node->getSymbolReference();
TR::SymbolReference *vecSymRef = pSPMDInfo->getVectorSymRef(symRef);
TR_ASSERT_FATAL(vectorOpCode != TR::BadILOp, "BAD IL Opcode to be assigned during transformation");
if (isCheckMode && !comp->cg()->getSupportsOpCodeForAutoSIMD(vectorOpCode, node->getDataType(), VECTOR_LENGTH))
return false;
if (!isCheckMode)
{
bool createdNewVecSym = false;
if (vecSymRef == NULL)
{
vecSymRef = comp->cg()->allocateLocalTemp(node->getDataType().scalarToVector(TR::VectorLength128)); // need to handle alignment?
pSPMDInfo->addVectorSymRef(symRef, vecSymRef);
createdNewVecSym = true;
if (trace)
traceMsg(comp, " created new symRef #%d for #%d\n", vecSymRef->getReferenceNumber(), symRef->getReferenceNumber());
}
if (trace)
traceMsg(comp, " using symRef #%d for #%d\n", vecSymRef->getReferenceNumber(), symRef->getReferenceNumber());
if (createdNewVecSym && reductionHashTab->locate(symRef, id))
{
TR_SPMDReductionInfo* reductionInfo = (TR_SPMDReductionInfo*)reductionHashTab->getData(id);
if (reductionInfo->reductionOp != Reduction_Invalid)
{
if (trace) traceMsg(comp, " node: %p is a store to a reduction var\n", node);
//creating trees to initialize reduction vector symref
reductionLoopEntranceProcessing(comp, loop, symRef, vecSymRef, reductionInfo->reductionOp);
//creating trees to transfer reduction vector symref data back to scalar symref
//also performs the combining operation when converting the vector symref to a scalar one
reductionLoopExitProcessing(comp, loop, symRef, vecSymRef, reductionInfo->reductionOp);
}
}
node->setSymbolReference(vecSymRef);
TR::Node::recreate(node, vectorOpCode);
}
return visitNodeToSIMDize(node, 0, node->getFirstChild(), pSPMDInfo, isCheckMode, loop, comp, usesInLoop, useNodesOfDefsInLoop, useDefInfo, defsInLoop, reductionHashTab, node->getSymbolReference());
}
}
else if (node->getOpCodeValue() == TR::asynccheck)
{
/*
* By default, loops with asynccheck nodes are not supported for AutoSIMD.
* If TR_enableAutoSIMDSkipAsynccheck is set, the asynccheck nodes will be removed from the loop while vectorizing it.
*/
static bool enableAutoSIMDSkipAsynccheck = feGetEnv("TR_enableAutoSIMDSkipAsynccheck") ? true : false;
if (enableAutoSIMDSkipAsynccheck)
{
if (!isCheckMode)
{
dumpOptDetails(comp, "Removing asynccheck. TreeTop: %p, node: %p\n", tt, node);
optimizer()->prepareForTreeRemoval(tt);
TR::TransformUtil::removeTree(comp, tt);
}
return true;
}
else
{
if (trace) traceMsg(comp, "asynccheck nodes are not supported for AutoSIMD. node: %p\n", node);
return false;
}
}
else if (scalarOp.isBranch() || node->getOpCodeValue()==TR::BBEnd || node->getOpCodeValue()==TR::BBStart ||
(node->getOpCodeValue()==TR::compressedRefs && node->getFirstChild()->getOpCode().isLoad()))
{
//Compressed ref treetops with a load can be ignored due to the load
// either being present under another tree top in the loop, which
// will be processed, or not used at all. Stores under a compressed ref
// tree top, will need to be handled differently
//ignore
return true;
}
else
{ //unsupported
return false;
}
return false;
}
TR::Block *findLoopInvariantBlockSIMD(TR::Compilation *comp, TR_RegionStructure *loop);
TR::Block *createLoopInvariantBlockSIMD(TR::Compilation *comp, TR_RegionStructure *loop);
bool TR_SPMDKernelParallelizer::visitNodeToSIMDize(TR::Node *parent, int32_t childIndex, TR::Node *node, TR_SPMDKernelInfo *pSPMDInfo, bool isCheckMode, TR_RegionStructure *loop, TR::Compilation *comp, SharedSparseBitVector *usesInLoop, CS2::ArrayOf<TR::Node *, TR::Allocator> &useNodesOfDefsInLoop, TR_UseDefInfo *useDefInfo, SharedSparseBitVector &defsInLoop, TR_HashTab* reductionHashTab, TR::SymbolReference* storeSymRef)
{
if (_visitedNodes.isSet(node->getGlobalIndex()))
return true;
_visitedNodes.set(node->getGlobalIndex());
bool trace = comp->trace(OMR::SPMDKernelParallelization);
TR::SymbolReference *piv = pSPMDInfo->getInductionVariableSymRef();
TR::ILOpCode scalarOp = node->getOpCode();
TR::ILOpCodes vectorOpCode = TR::ILOpCode::convertScalarToVector(scalarOp.getOpCodeValue());
int32_t pivStride = INVALID_STRIDE;
if (trace)
{
traceMsg(comp," Visiting Node [%p] during %s mode - %s\n", node, isCheckMode ? "detection" : "transformation", scalarOp.getName());
}
TR_HashId id = 0;
_loopDataType->locate(loop,id);
if (isCheckMode && node->getSize() != ((TR::Node *)_loopDataType->getData(id))->getSize())
{
if (trace) traceMsg(comp," Node size does not match loop data type for node: %p\n", node);
return false;
}
if (loop->isExprInvariant(node))
{
if (!isCheckMode)
genVectorAccessForScalar(parent, childIndex, node);
return true;
}
if (isCheckMode)
(*usesInLoop)[node->getGlobalIndex()] = true;
//If we get BadIlOP during transformation, we can either return half transformed trees or set BadIlOp. Half transformed trees are harder
//to debug in codegen and can happen due to multiple reasons. So for easy of debugging, we go ahead and set BadIlOp.
if (isCheckMode && vectorOpCode == TR::BadILOp)
{
if (trace)
{
traceMsg(comp," [%p]: Can't convert scalar OpCode %s to a vectorized instruction\n", node, scalarOp.getName());
}
return false;
}
TR_ASSERT(vectorOpCode != TR::BadILOp, "BAD IL Opcode to be assigned during transformation");
if (isCheckMode && !comp->cg()->getSupportsOpCodeForAutoSIMD(vectorOpCode, node->getDataType(), VECTOR_LENGTH))
{
if (trace)
{
traceMsg(comp," [%p - %s]: vector Opcode and data type are not supported by this platform\n", node, scalarOp.getName());
}
return false;
}
TR::ILOpCode vectorOp;
vectorOp.setOpCodeValue(vectorOpCode);
if (scalarOp.isLoadVar())
{
if (isCheckMode)
{
if (!scalarOp.isLoadIndirect())
{
bool loadInductionVar = false;
// handle expressions using the induction variable itself
for (int32_t iv=0;iv<_pivList.NumberOfElements();iv++)
{
if (node->getSymbolReference()==_pivList[iv]->getSymRef())
{
loadInductionVar = true;
break;
}
}
if (loadInductionVar)
{
// confirm platform supports vectorizing PIV uses
bool platformSupport = comp->cg()->getSupportsOpCodeForAutoSIMD(TR::vstore, node->getDataType(), VECTOR_LENGTH);
platformSupport = platformSupport && comp->cg()->getSupportsOpCodeForAutoSIMD(TR::vsetelem, node->getDataType(), VECTOR_LENGTH);
platformSupport = platformSupport && comp->cg()->getSupportsOpCodeForAutoSIMD(TR::vadd, node->getDataType(), VECTOR_LENGTH);
platformSupport = platformSupport && comp->cg()->getSupportsOpCodeForAutoSIMD(TR::vsplats, node->getDataType(), VECTOR_LENGTH);
if (trace && platformSupport)
traceMsg(comp, " Found use of induction variable at node [%p]\n", node);
if (trace && !platformSupport)
traceMsg(comp, " Found use of induction variable at node [%p] - platform does not support this vectorization\n", node);
if (trace && platformSupport)
traceMsg(comp, " Found use of induction variable at node [%p] - vectorization disabled for now\n", node);
return false; // see : eclipse-openj9/openj9/9446
}
}
}
if (!isCheckMode)
{
if (scalarOp.isLoadIndirect() && !hasPIV(node, piv)) // SIMD_TODO: strictly speaking should check for stride == 0
{
genVectorAccessForScalar(parent, childIndex, node);
return true;
}
TR::SymbolReference *symRef = node->getSymbolReference();
TR::SymbolReference *vecSymRef = pSPMDInfo->getVectorSymRef(symRef);
bool createdNewVecSym = false;
if (!vecSymRef)
{
// TODO: use best vector length available
vecSymRef = scalarOp.isLoadIndirect() ?
comp->getSymRefTab()->findOrCreateArrayShadowSymbolRef(node->getDataType().scalarToVector(TR::VectorLength128), NULL)
: vecSymRef = comp->cg()->allocateLocalTemp(node->getDataType().scalarToVector(TR::VectorLength128)); // need to handle alignment?
pSPMDInfo->addVectorSymRef(symRef, vecSymRef);
createdNewVecSym = true;
if (trace)
traceMsg(comp, " created new symRef #%d for #%d\n", vecSymRef->getReferenceNumber(), symRef->getReferenceNumber());
}
if (trace)
traceMsg(comp, " using symRef #%d for #%d\n", vecSymRef->getReferenceNumber(), symRef->getReferenceNumber());
bool loadInductionVar = false;
if (!scalarOp.isLoadIndirect())
{
// handle expressions using the induction variable itself
for (int32_t iv=0;iv<_pivList.NumberOfElements();iv++)
{
if (node->getSymbolReference() == _pivList[iv]->getSymRef())
{
loadInductionVar = true;
break;
}
}
}
if (loadInductionVar && createdNewVecSym)
{
// initializing the vectorized version of the induction variable
pSPMDInfo->setIsPIVVectorized(true);
TR::Block* loopInvariantBlock = findLoopInvariantBlockSIMD(comp, loop);
if (!loopInvariantBlock)
{
loopInvariantBlock = createLoopInvariantBlockSIMD(comp, loop);
}
TR::Node *splatsNode = TR::Node::create(TR::vsplats, 1, node->duplicateTree());
TR::Node *vconstNode = TR::Node::create(TR::vsplats, 1, TR::Node::create(TR::iconst, 0, 0));
TR::Node *vsetelem1Node = TR::Node::create(TR::vsetelem, 3);
vsetelem1Node->setAndIncChild(0, vconstNode);
vsetelem1Node->setAndIncChild(1, TR::Node::create(TR::iconst, 0, 1));
vsetelem1Node->setAndIncChild(2, TR::Node::create(TR::iconst, 0, 1));
TR::Node *vsetelem2Node = TR::Node::create(TR::vsetelem, 3);
vsetelem2Node->setAndIncChild(0, vsetelem1Node);
vsetelem2Node->setAndIncChild(1, TR::Node::create(TR::iconst, 0, 2));
vsetelem2Node->setAndIncChild(2, TR::Node::create(TR::iconst, 0, 2));
TR::Node *vsetelem3Node = TR::Node::create(TR::vsetelem, 3);
vsetelem3Node->setAndIncChild(0, vsetelem2Node);
vsetelem3Node->setAndIncChild(1, TR::Node::create(TR::iconst, 0, 3));
vsetelem3Node->setAndIncChild(2, TR::Node::create(TR::iconst, 0, 3));
TR::Node *vaddNode = TR::Node::create(TR::vadd, 2);
vaddNode->setAndIncChild(0, splatsNode);
vaddNode->setAndIncChild(1, vsetelem3Node);
TR::Node *vstoreNode = TR::Node::createWithSymRef(TR::vstore, 1, 1, vaddNode, vecSymRef);
TR::TreeTop *insertionPoint = loopInvariantBlock->getEntry();
TR::Node *treetopNode = TR::Node::create(TR::treetop, 1, vstoreNode);
TR::TreeTop *vinitTreeTop = TR::TreeTop::create(comp, treetopNode, 0, 0);
insertionPoint->insertAfter(vinitTreeTop);
if (trace)
traceMsg(comp, " Created trees to initialize vectorized PIV at node [%p]\n", vstoreNode);
}
if (loadInductionVar)
{
// the load op for the PIV is usually commoned with address calculations
// so uncommoning it so it can be vectorized without touching address calc
TR::Node *vloadNode = node->duplicateTree();
node->recursivelyDecReferenceCount();
// can visit the commoned node again, if needed.
_visitedNodes.reset(node->getGlobalIndex());
TR::Node::recreate(vloadNode, vectorOpCode);
vloadNode->setSymbolReference(vecSymRef);
parent->setAndIncChild(childIndex, vloadNode);
if (trace)
{
traceMsg(comp, " Vectorizing PIV use at node [%p]\n", vloadNode);
traceMsg(comp, "Transforming node [%p] from %s to %s\n", node, scalarOp.getName(), vectorOp.getName());
}
}
else
{
TR::Node::recreate(node, vectorOpCode);
node->setSymbolReference(vecSymRef);
}
//handling initialization of reduction symRefs
if (!scalarOp.isLoadIndirect())
{
if (createdNewVecSym && reductionHashTab->locate(node->getSymbolReference(), id))
{
TR_SPMDReductionInfo* reductionInfo = (TR_SPMDReductionInfo*)reductionHashTab->getData(id);
if (reductionInfo->reductionOp != Reduction_Invalid)
{
if (trace) traceMsg(comp, " node: %p is a load from a reduction var\n", node);
//creating trees to initialize reduction vector symref
reductionLoopEntranceProcessing(comp, loop, symRef, vecSymRef, reductionInfo->reductionOp);
//creating trees to transfer reduction vector symref data back to scalar symref
//also performs the combining operation when converting the vector symref to a scalar one
reductionLoopExitProcessing(comp, loop, symRef, vecSymRef, reductionInfo->reductionOp);
}
}
}
return true;
}
if (scalarOp.isLoadIndirect())
{
int32_t pivStride = INVALID_STRIDE;
bool affine = isAffineAccess(comp, node->getFirstChild(), loop, piv, pivStride);
if (trace)
traceMsg(comp, " node %p affine = %d stride = %d\n", node, affine, pivStride);
if (!affine || !(pivStride*getUnrollCount(node->getDataType()) == VECTOR_SIZE || pivStride == 0))
{
return false;
}
}
else
{
if (reductionHashTab->locate(node->getSymbolReference(), id))
{
TR_SPMDReductionInfo* reductionInfo = (TR_SPMDReductionInfo*)reductionHashTab->getData(id);
//reduction symRefs can only be read from a statement that also stores back to the same symRef (eg. sum = sum + a[i])
//this code checks that this condition is being met. If not, the symRef is not a supported reduction symRef
if (reductionInfo->reductionOp != Reduction_Invalid && node->getSymbolReference() != storeSymRef)
{
if (trace) traceMsg(comp, " visitNodeToSIMDize: Load symRef does not match store symref at node: %p\n", node);
reductionInfo->reductionOp = Reduction_Invalid;
ListIterator<TR::Node> nodeIt(&reductionInfo->storeNodes);
for (TR::Node *nextNode = nodeIt.getCurrent(); nextNode; nextNode=nodeIt.getNext())
{
if (trace) traceMsg(comp, " visitNodeToSIMDize: Adding recorded invalid reduction node to defsInLoop. node: %p\n", nextNode);
defsInLoop[nextNode->getGlobalIndex()] = true;
collectUses(nextNode, comp, useDefInfo, useNodesOfDefsInLoop);
}
}
}
else
{
if (trace) traceMsg(comp, " visitNodeToSIMDize: Never before seen symRef being recorded as not a reduction at node: %p\n", node);
TR_SPMDReductionInfo* reductionInfo = new (comp->trStackMemory()) TR_SPMDReductionInfo(comp);
reductionInfo->reductionOp = Reduction_Invalid;
reductionInfo->reductionSymRef = node->getSymbolReference();
reductionHashTab->add(node->getSymbolReference(), id, reductionInfo);
}
}
return true;
}
else
{
for (int32_t i = 0; i < node->getNumChildren(); i++)
{
if (!visitNodeToSIMDize(node, i, node->getChild(i), pSPMDInfo, isCheckMode, loop, comp, usesInLoop, useNodesOfDefsInLoop, useDefInfo, defsInLoop, reductionHashTab, storeSymRef))
return false;
}
if (scalarOp.isAdd() || scalarOp.isSub() || scalarOp.isMul() || scalarOp.isDiv() || scalarOp.isRem() || scalarOp.isLeftShift() || scalarOp.isRightShift() || scalarOp.isShiftLogical() || scalarOp.isAnd() || scalarOp.isXor() || scalarOp.isOr())
{
if (isCheckMode)
return true;
if (trace)
traceMsg(comp, "Transforming node [%p] from %s to %s\n", node, scalarOp.getName(), vectorOp.getName());
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
while (firstChild->getOpCodeValue() == TR::PassThrough) firstChild = firstChild->getFirstChild();
while (secondChild->getOpCodeValue() == TR::PassThrough) secondChild = secondChild->getFirstChild();
TR_ASSERT(firstChild->getDataType().isVector() && firstChild->getDataType() == secondChild->getDataType()," Both children of the node to be transformed must be vector types %s %s", firstChild->getOpCode().getName(), secondChild->getOpCode().getName());
TR::Node::recreate(node, vectorOpCode);
return true;
}
if (scalarOp.isNeg() ||
scalarOp.getOpCodeValue() == TR::l2d)
{
if (isCheckMode)
return true;
if (trace)
traceMsg(comp, "Transforming node [%p] from %s to %s\n", node, scalarOp.getName(), vectorOp.getName());
TR::Node *firstChild = node->getFirstChild();
while (firstChild->getOpCodeValue() == TR::PassThrough) firstChild = firstChild->getFirstChild();
TR_ASSERT(firstChild->getDataType().isVector()," Child of the node to be transformed must be a vector type");
TR::Node::recreate(node, vectorOpCode);
return true;
}
}
if (trace)
{
traceMsg(comp," [%p - %s]: Vectorization failed due to unknown reason.\n", node, scalarOp.getName());
}
return false;
}
bool TR_SPMDKernelParallelizer::autoSIMDReductionSupported(TR::Compilation *comp, TR::Node *node)
{
bool trace = comp->trace(OMR::SPMDKernelParallelization);
//float and double not currently supported.
static bool enableFPAutoSIMDReduction = feGetEnv("TR_enableFPAutoSIMDReduction") ? true : false;
if (!enableFPAutoSIMDReduction
&& !_fpreductionAnnotation
&& (node->getDataType() == TR::Float || node->getDataType() == TR::Double))
{
if (trace) traceMsg(comp, " autoSIMDReductionSupported: float and double reduction are not supported right now. node: %p\n", node);
return false;
}