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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-2…
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…0180116' into staging

target-arm queue:
 * SDHCI: cleanups and minor bug fixes
 * target/arm: minor refactor preparatory to fp16 support
 * omap_ssd, ssi-sd, pl181, milkymist-memcard: reset the SD
   card on controller reset (fixes migration failures)
 * target/arm: Handle page table walk load failures correctly
 * hw/arm/virt: Add virt-2.12 machine type
 * get_phys_addr_pmsav7: Support AP=0b111 for v7M
 * hw/intc/armv7m: Support byte and halfword accesses to CFSR

# gpg: Signature made Tue 16 Jan 2018 13:33:31 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180116: (24 commits)
  sdhci: add a 'dma' property to the sysbus devices
  sdhci: fix the PCI device, using the PCI address space for DMA
  sdhci: Implement write method of ACMD12ERRSTS register
  sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only
  sdhci: rename the SDHC_CAPAB register
  sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h"
  sdhci: convert the DPRINT() calls into trace events
  sdhci: use qemu_log_mask(UNIMP) instead of fprintf()
  sdhci: refactor common sysbus/pci unrealize() into sdhci_common_unrealize()
  sdhci: refactor common sysbus/pci realize() into sdhci_common_realize()
  sdhci: refactor common sysbus/pci class_init() into sdhci_common_class_init()
  sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties
  sdhci: remove dead code
  sdhci: clean up includes
  target/arm: Add fp16 support to vfp_expand_imm
  target/arm: Split out vfp_expand_imm
  hw/sd/omap_mmc: Reset SD card on controller reset
  hw/sd/ssi-sd: Reset SD card on controller reset
  hw/sd/milkymist-memcard: Reset SD card on controller reset
  hw/sd/pl181: Reset SD card on controller reset
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@pm215
pm215 committed Jan 16, 2018
2 parents f521eee + 60765b6 commit aae39d2
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Showing 14 changed files with 362 additions and 167 deletions.
19 changes: 17 additions & 2 deletions hw/arm/virt.c
View file
Expand Up @@ -1618,7 +1618,7 @@ static void machvirt_machine_init(void)
}
type_init(machvirt_machine_init);

static void virt_2_11_instance_init(Object *obj)
static void virt_2_12_instance_init(Object *obj)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
Expand Down Expand Up @@ -1678,10 +1678,25 @@ static void virt_2_11_instance_init(Object *obj)
vms->irqmap = a15irqmap;
}

static void virt_machine_2_12_options(MachineClass *mc)
{
}
DEFINE_VIRT_MACHINE_AS_LATEST(2, 12)

#define VIRT_COMPAT_2_11 \
HW_COMPAT_2_11

static void virt_2_11_instance_init(Object *obj)
{
virt_2_12_instance_init(obj);
}

static void virt_machine_2_11_options(MachineClass *mc)
{
virt_machine_2_12_options(mc);
SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11);
}
DEFINE_VIRT_MACHINE_AS_LATEST(2, 11)
DEFINE_VIRT_MACHINE(2, 11)

#define VIRT_COMPAT_2_10 \
HW_COMPAT_2_10
Expand Down
38 changes: 22 additions & 16 deletions hw/intc/armv7m_nvic.c
View file
Expand Up @@ -896,13 +896,6 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
val |= (1 << 8);
}
return val;
case 0xd28: /* Configurable Fault Status. */
/* The BFSR bits [15:8] are shared between security states
* and we store them in the NS copy
*/
val = cpu->env.v7m.cfsr[attrs.secure];
val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
return val;
case 0xd2c: /* Hard Fault Status. */
return cpu->env.v7m.hfsr;
case 0xd30: /* Debug Fault Status. */
Expand Down Expand Up @@ -1280,15 +1273,6 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
nvic_irq_update(s);
break;
case 0xd28: /* Configurable Fault Status. */
cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */
if (attrs.secure) {
/* The BFSR bits [15:8] are shared between security states
* and we store them in the NS copy.
*/
cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
}
break;
case 0xd2c: /* Hard Fault Status. */
cpu->env.v7m.hfsr &= ~value; /* W1C */
break;
Expand Down Expand Up @@ -1667,6 +1651,14 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
}
break;
case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
/* The BFSR bits [15:8] are shared between security states
* and we store them in the NS copy
*/
val = s->cpu->env.v7m.cfsr[attrs.secure];
val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
val = extract32(val, (offset - 0xd28) * 8, size * 8);
break;
case 0xfe0 ... 0xfff: /* ID. */
if (offset & 3) {
val = 0;
Expand Down Expand Up @@ -1765,6 +1757,20 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
}
nvic_irq_update(s);
return MEMTX_OK;
case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
/* All bits are W1C, so construct 32 bit value with 0s in
* the parts not written by the access size
*/
value <<= ((offset - 0xd28) * 8);

s->cpu->env.v7m.cfsr[attrs.secure] &= ~value;
if (attrs.secure) {
/* The BFSR bits [15:8] are shared between security states
* and we store them in the NS copy.
*/
s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
}
return MEMTX_OK;
}
if (size == 4) {
nvic_writel(s, offset, value, attrs);
Expand Down
4 changes: 4 additions & 0 deletions hw/sd/milkymist-memcard.c
View file
Expand Up @@ -248,6 +248,10 @@ static void milkymist_memcard_reset(DeviceState *d)
for (i = 0; i < R_MAX; i++) {
s->regs[i] = 0;
}
/* Since we're still using the legacy SD API the card is not plugged
* into any bus, and we must reset it manually.
*/
device_reset(DEVICE(s->card));
}

static int milkymist_memcard_init(SysBusDevice *dev)
Expand Down
14 changes: 10 additions & 4 deletions hw/sd/omap_mmc.c
View file
Expand Up @@ -305,6 +305,12 @@ void omap_mmc_reset(struct omap_mmc_s *host)
host->cdet_enable = 0;
qemu_set_irq(host->coverswitch, host->cdet_state);
host->clkdiv = 0;

/* Since we're still using the legacy SD API the card is not plugged
* into any bus, and we must reset it manually. When omap_mmc is
* QOMified this must move into the QOM reset function.
*/
device_reset(DEVICE(host->card));
}

static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
Expand Down Expand Up @@ -587,8 +593,6 @@ struct omap_mmc_s *omap_mmc_init(hwaddr base,
s->lines = 1; /* TODO: needs to be settable per-board */
s->rev = 1;

omap_mmc_reset(s);

memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
memory_region_add_subregion(sysmem, base, &s->iomem);

Expand All @@ -598,6 +602,8 @@ struct omap_mmc_s *omap_mmc_init(hwaddr base,
exit(1);
}

omap_mmc_reset(s);

return s;
}

Expand All @@ -613,8 +619,6 @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
s->lines = 4;
s->rev = 2;

omap_mmc_reset(s);

memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
Expand All @@ -628,6 +632,8 @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
sd_set_cb(s->card, NULL, s->cdet);

omap_mmc_reset(s);

return s;
}

Expand Down
4 changes: 4 additions & 0 deletions hw/sd/pl181.c
View file
Expand Up @@ -480,6 +480,10 @@ static void pl181_reset(DeviceState *d)

/* We can assume our GPIO outputs have been wired up now */
sd_set_cb(s->card, s->cardstatus[0], s->cardstatus[1]);
/* Since we're still using the legacy SD API the card is not plugged
* into any bus, and we must reset it manually.
*/
device_reset(DEVICE(s->card));
}

static void pl181_init(Object *obj)
Expand Down
7 changes: 2 additions & 5 deletions hw/sd/sdhci-internal.h
View file
Expand Up @@ -24,8 +24,6 @@
#ifndef SDHCI_INTERNAL_H
#define SDHCI_INTERNAL_H

#include "hw/sd/sdhci.h"

/* R/W SDMA System Address register 0x0 */
#define SDHC_SYSAD 0x00

Expand All @@ -45,6 +43,7 @@
#define SDHC_TRNS_ACMD12 0x0004
#define SDHC_TRNS_READ 0x0010
#define SDHC_TRNS_MULTI 0x0020
#define SDHC_TRNMOD_MASK 0x0037

/* R/W Command Register 0x0 */
#define SDHC_CMDREG 0x0E
Expand Down Expand Up @@ -175,7 +174,7 @@
#define SDHC_ACMD12ERRSTS 0x3C

/* HWInit Capabilities Register 0x05E80080 */
#define SDHC_CAPAREG 0x40
#define SDHC_CAPAB 0x40
#define SDHC_CAN_DO_DMA 0x00400000
#define SDHC_CAN_DO_ADMA2 0x00080000
#define SDHC_CAN_DO_ADMA1 0x00100000
Expand Down Expand Up @@ -227,6 +226,4 @@ enum {
sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */
};

extern const VMStateDescription sdhci_vmstate;

#endif

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