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SingleCoreProcessor.par
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SingleCoreProcessor.par
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Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
filipeslaptop:: Mon Apr 11 16:00:58 2016
par -w -intstyle ise -ol high -mt off SingleCoreProcessor_map.ncd
SingleCoreProcessor.ncd SingleCoreProcessor.pcf
Constraints file: SingleCoreProcessor.pcf.
Loading device for application Rf_Device from file '7k70t.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"SingleCoreProcessor" is an NCD, version 3.2, device xc7k70t, package fbg676, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.970 Volts. (default - Range: 0.970 to 1.030 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.10 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 1,385 out of 82,000 1%
Number used as Flip Flops: 1,385
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 2,220 out of 41,000 5%
Number used as logic: 2,219 out of 41,000 5%
Number using O6 output only: 2,084
Number using O5 output only: 1
Number using O5 and O6: 134
Number used as ROM: 0
Number used as Memory: 0 out of 13,400 0%
Number used exclusively as route-thrus: 1
Number with same-slice register load: 1
Number with same-slice carry load: 0
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,232 out of 10,250 12%
Number of LUT Flip Flop pairs used: 3,094
Number with an unused Flip Flop: 1,719 out of 3,094 55%
Number with an unused LUT: 874 out of 3,094 28%
Number of fully used LUT-FF pairs: 501 out of 3,094 16%
Number of slice register sites lost
to control set restrictions: 0 out of 82,000 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 67 out of 300 22%
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 16 out of 135 11%
Number using RAMB36E1 only: 16
Number using FIFO36E1 only: 0
Number of RAMB18E1/FIFO18E1s: 0 out of 270 0%
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
Number used as BUFGs: 1
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 300 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 300 0%
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0 out of 100 0%
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 300 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 24 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 24 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 96 0%
Number of BUFRs: 0 out of 24 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 4 out of 240 1%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of GTXE2_CHANNELs: 0 out of 8 0%
Number of GTXE2_COMMONs: 0 out of 2 0%
Number of IBUFDS_GTE2s: 0 out of 4 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 6 0%
Number of IN_FIFOs: 0 out of 24 0%
Number of MMCME2_ADVs: 0 out of 6 0%
Number of OUT_FIFOs: 0 out of 24 0%
Number of PCIE_2_1s: 0 out of 1 0%
Number of PHASER_REFs: 0 out of 6 0%
Number of PHY_CONTROLs: 0 out of 6 0%
Number of PLLE2_ADVs: 0 out of 6 0%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 38 secs
Finished initial Timing Analysis. REAL time: 38 secs
Starting Router
Phase 1 : 17546 unrouted; REAL time: 41 secs
Phase 2 : 15739 unrouted; REAL time: 43 secs
Phase 3 : 6727 unrouted; REAL time: 56 secs
Phase 4 : 6725 unrouted; (Par is working to improve performance) REAL time: 1 mins 3 secs
Updating file: SingleCoreProcessor.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 1 mins 20 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 1 mins 20 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 1 mins 20 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 1 mins 20 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 1 mins 31 secs
Total REAL time to Router completion: 1 mins 31 secs
Total CPU time to Router completion: 1 mins 34 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 13.028ns| N/A| 0
_BUFGP | HOLD | 0.023ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 1 mins 38 secs
Total CPU time to PAR completion: 1 mins 41 secs
Peak Memory Usage: 1034 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2
Writing design to file SingleCoreProcessor.ncd
PAR done!