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SingleCoreProcessor.syr
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SingleCoreProcessor.syr
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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.10 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.10 secs
-->
Reading design: SingleCoreProcessor.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "SingleCoreProcessor.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "SingleCoreProcessor"
Output Format : NGC
Target Device : xc7k70t-2-fbg676
---- Source Options
Top Module Name : SingleCoreProcessor
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "/home/nuno/aac/aac/lab1/main_definitions.vhd" into library work
Parsing package <main_definitions>.
Parsing package body <main_definitions>.
Parsing VHDL file "/home/nuno/aac/aac/lab1/register_file.vhd" into library work
Parsing entity <register_file>.
Parsing architecture <Behavioral> of entity <register_file>.
Parsing VHDL file "/home/nuno/aac/aac/lab1/decoder.vhd" into library work
Parsing entity <decoder>.
Parsing architecture <Behavioral> of entity <decoder>.
Parsing VHDL file "/home/nuno/aac/aac/lab1/branch_control.vhd" into library work
Parsing entity <branch_control>.
Parsing architecture <Behavioral> of entity <branch_control>.
Parsing VHDL file "/home/nuno/aac/aac/lab1/alu.vhd" into library work
Parsing entity <alu>.
Parsing architecture <Behavioral> of entity <alu>.
Parsing VHDL file "/home/nuno/aac/aac/lab1/simpleDualPortMemory.vhd" into library work
Parsing entity <DualPortMemory>.
Parsing architecture <Behavioral> of entity <dualportmemory>.
Parsing VHDL file "/home/nuno/aac/aac/lab1/simpleCore.vhd" into library work
Parsing entity <simpleCore>.
Parsing architecture <Behavioral> of entity <simplecore>.
Parsing VHDL file "/home/nuno/aac/aac/lab1/SingleCoreProcessor.vhd" into library work
Parsing entity <SingleCoreProcessor>.
Parsing architecture <Behavioral> of entity <singlecoreprocessor>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <SingleCoreProcessor> (architecture <Behavioral>) from library <work>.
Elaborating entity <simpleCore> (architecture <Behavioral>) from library <work>.
Elaborating entity <decoder> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/nuno/aac/aac/lab1/simpleCore.vhd" Line 271: Assignment to brali_fw ignored, since the identifier is never used
Elaborating entity <register_file> (architecture <Behavioral>) from library <work>.
Elaborating entity <branch_control> (architecture <Behavioral>) from library <work>.
Elaborating entity <alu> (architecture <Behavioral>) from library <work>.
Elaborating entity <DualPortMemory> (architecture <Behavioral>) from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <SingleCoreProcessor>.
Related source file is "/home/nuno/aac/aac/lab1/SingleCoreProcessor.vhd".
Summary:
no macro.
Unit <SingleCoreProcessor> synthesized.
Synthesizing Unit <simpleCore>.
Related source file is "/home/nuno/aac/aac/lab1/simpleCore.vhd".
Found 16-bit register for signal <ID_PC>.
Found 16-bit register for signal <REG_PC>.
Found 32-bit register for signal <REG_I>.
Found 32-bit register for signal <EX_OpD>.
Found 32-bit register for signal <MEM_ExResult>.
Found 32-bit register for signal <MEM_DataIn>.
Found 32-bit register for signal <WB_ExResult>.
Found 32-bit register for signal <WB_StoreData>.
Found 5-bit register for signal <WB_ID_OpD>.
Found 5-bit register for signal <MEM_ID_OpD>.
Found 5-bit register for signal <EX_ID_OpD>.
Found 3-bit register for signal <EX_CTRL>.
Found 3-bit register for signal <MEM_CTRL>.
Found 3-bit register for signal <WB_MemCTRL>.
Found 33-bit register for signal <EX_OpA>.
Found 33-bit register for signal <EX_OpB>.
Found 1-bit register for signal <BrTaken>.
Found 1-bit register for signal <EX_OpC>.
Found 1-bit register for signal <MEM_RegWE>.
Found 1-bit register for signal <RegWE>.
Found 1-bit register for signal <ID_STAGE_ENABLE>.
Found 16-bit register for signal <REG_PC[15]_dff_0>.
Found 1-bit register for signal <MSR_C_REG>.
Found 1-bit register for signal <Hazard>.
Found 1-bit register for signal <EX_MSR_C_WE>.
Found 3-bit register for signal <EX_MemCTRL>.
Found 1-bit register for signal <EX_RegWE>.
Summary:
inferred 342 D-type flip-flop(s).
inferred 29 Multiplexer(s).
Unit <simpleCore> synthesized.
Synthesizing Unit <decoder>.
Related source file is "/home/nuno/aac/aac/lab1/decoder.vhd".
Found 16-bit register for signal <RImm16>.
Found 1-bit register for signal <MSR_I>.
Summary:
inferred 17 D-type flip-flop(s).
inferred 86 Multiplexer(s).
Unit <decoder> synthesized.
Synthesizing Unit <register_file>.
Related source file is "/home/nuno/aac/aac/lab1/register_file.vhd".
Found 32-bit register for signal <exTable>.
Found 32-bit register for signal <memTable>.
Found 32-bit register for signal <wbTable>.
Found 32-bit register for signal <RegisterTable<1>>.
Found 32-bit register for signal <RegisterTable<2>>.
Found 32-bit register for signal <RegisterTable<3>>.
Found 32-bit register for signal <RegisterTable<4>>.
Found 32-bit register for signal <RegisterTable<5>>.
Found 32-bit register for signal <RegisterTable<6>>.
Found 32-bit register for signal <RegisterTable<7>>.
Found 32-bit register for signal <RegisterTable<8>>.
Found 32-bit register for signal <RegisterTable<9>>.
Found 32-bit register for signal <RegisterTable<10>>.
Found 32-bit register for signal <RegisterTable<11>>.
Found 32-bit register for signal <RegisterTable<12>>.
Found 32-bit register for signal <RegisterTable<13>>.
Found 32-bit register for signal <RegisterTable<14>>.
Found 32-bit register for signal <RegisterTable<15>>.
Found 32-bit register for signal <RegisterTable<16>>.
Found 32-bit register for signal <RegisterTable<17>>.
Found 32-bit register for signal <RegisterTable<18>>.
Found 32-bit register for signal <RegisterTable<19>>.
Found 32-bit register for signal <RegisterTable<20>>.
Found 32-bit register for signal <RegisterTable<21>>.
Found 32-bit register for signal <RegisterTable<22>>.
Found 32-bit register for signal <RegisterTable<23>>.
Found 32-bit register for signal <RegisterTable<24>>.
Found 32-bit register for signal <RegisterTable<25>>.
Found 32-bit register for signal <RegisterTable<26>>.
Found 32-bit register for signal <RegisterTable<27>>.
Found 32-bit register for signal <RegisterTable<28>>.
Found 32-bit register for signal <RegisterTable<29>>.
Found 32-bit register for signal <RegisterTable<30>>.
Found 32-bit register for signal <RegisterTable<31>>.
Found 1-bit register for signal <loadOP_reg>.
Found 1-bit 32-to-1 multiplexer for signal <FW_exTable_A> created at line 107.
Found 1-bit 32-to-1 multiplexer for signal <FW_memTable_A> created at line 108.
Found 1-bit 32-to-1 multiplexer for signal <FW_wbTable_A> created at line 109.
Found 1-bit 32-to-1 multiplexer for signal <FW_exTable_B> created at line 110.
Found 1-bit 32-to-1 multiplexer for signal <FW_memTable_B> created at line 111.
Found 1-bit 32-to-1 multiplexer for signal <FW_wbTable_B> created at line 112.
Found 1-bit 32-to-1 multiplexer for signal <OpD[4]_exTable[31]_Mux_48_o> created at line 119.
Found 1-bit 32-to-1 multiplexer for signal <OpD[4]_memTable[31]_Mux_49_o> created at line 119.
Found 1-bit 32-to-1 multiplexer for signal <OpD[4]_wbTable[31]_Mux_50_o> created at line 119.
Found 32-bit 32-to-1 multiplexer for signal <DoutA> created at line 122.
Found 32-bit 32-to-1 multiplexer for signal <DoutB> created at line 123.
Found 32-bit 32-to-1 multiplexer for signal <DoutD> created at line 124.
Summary:
inferred 1089 D-type flip-flop(s).
inferred 12 Multiplexer(s).
Unit <register_file> synthesized.
Synthesizing Unit <branch_control>.
Related source file is "/home/nuno/aac/aac/lab1/branch_control.vhd".
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Data_Hazard> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <BrTakenReg>.
Found 16-bit adder for signal <PC[15]_PCIncrement[15]_add_16_OUT> created at line 88.
Found 16-bit adder for signal <RegPC[15]_PCIncrement[15]_add_18_OUT> created at line 87.
Found 16-bit adder for signal <PC[15]_GND_12_o_add_22_OUT> created at line 85.
Found 16-bit subtractor for signal <GND_12_o_GND_12_o_sub_18_OUT<15:0>> created at line 88.
Summary:
inferred 4 Adder/Subtractor(s).
inferred 1 D-type flip-flop(s).
inferred 11 Multiplexer(s).
Unit <branch_control> synthesized.
Synthesizing Unit <alu>.
Related source file is "/home/nuno/aac/aac/lab1/alu.vhd".
Found 34-bit adder for signal <n0160> created at line 90.
Found 34-bit adder for signal <uAddComp.auxRes> created at line 90.
Found 6-bit adder for signal <n0164> created at line 124.
Found 6-bit subtractor for signal <GND_14_o_GND_14_o_sub_49_OUT<5:0>> created at line 130.
Found 33x33-bit multiplier for signal <uMultiplier.auxRes> created at line 106.
Found 1-bit 21-to-1 multiplexer for signal <PWR_14_o_OpA[16]_Mux_31_o> created at line 124.
Found 1-bit 21-to-1 multiplexer for signal <PWR_14_o_OpA[15]_Mux_32_o> created at line 124.
Found 1-bit 24-to-1 multiplexer for signal <PWR_14_o_OpA[14]_Mux_33_o> created at line 124.
Found 1-bit 24-to-1 multiplexer for signal <PWR_14_o_OpA[13]_Mux_34_o> created at line 124.
Found 1-bit 25-to-1 multiplexer for signal <PWR_14_o_OpA[12]_Mux_35_o> created at line 124.
Found 1-bit 25-to-1 multiplexer for signal <PWR_14_o_OpA[11]_Mux_36_o> created at line 124.
Found 1-bit 27-to-1 multiplexer for signal <PWR_14_o_OpA[10]_Mux_37_o> created at line 124.
Found 1-bit 27-to-1 multiplexer for signal <PWR_14_o_OpA[9]_Mux_38_o> created at line 124.
Found 1-bit 28-to-1 multiplexer for signal <PWR_14_o_OpA[8]_Mux_39_o> created at line 124.
Found 1-bit 28-to-1 multiplexer for signal <PWR_14_o_OpA[7]_Mux_40_o> created at line 124.
Found 1-bit 30-to-1 multiplexer for signal <PWR_14_o_OpA[6]_Mux_41_o> created at line 124.
Found 1-bit 30-to-1 multiplexer for signal <PWR_14_o_OpA[5]_Mux_42_o> created at line 124.
Found 1-bit 31-to-1 multiplexer for signal <PWR_14_o_OpA[4]_Mux_43_o> created at line 124.
Found 1-bit 31-to-1 multiplexer for signal <PWR_14_o_OpA[3]_Mux_44_o> created at line 124.
Found 1-bit 32-to-1 multiplexer for signal <PWR_14_o_OpA[2]_Mux_45_o> created at line 124.
Found 1-bit 32-to-1 multiplexer for signal <PWR_14_o_OpA[1]_Mux_46_o> created at line 124.
Found 1-bit 32-to-1 multiplexer for signal <PWR_14_o_OpA[0]_Mux_47_o> created at line 124.
Found 32-bit 4-to-1 multiplexer for signal <logicRes> created at line 67.
Found 32-bit 3-to-1 multiplexer for signal <_n0202> created at line 46.
Summary:
inferred 1 Multiplier(s).
inferred 4 Adder/Subtractor(s).
inferred 218 Multiplexer(s).
Unit <alu> synthesized.
Synthesizing Unit <DualPortMemory>.
Related source file is "/home/nuno/aac/aac/lab1/simpleDualPortMemory.vhd".
WARNING:Xst:647 - Input <Addr_A<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Addr_B<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 16384x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.
Found 32-bit register for signal <DO_B>.
Found 32-bit register for signal <DO_A>.
Summary:
inferred 1 RAM(s).
inferred 64 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <DualPortMemory> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 1
16384x32-bit dual-port RAM : 1
# Multipliers : 1
33x33-bit multiplier : 1
# Adders/Subtractors : 8
16-bit adder : 3
16-bit subtractor : 1
34-bit adder : 2
6-bit adder : 1
6-bit subtractor : 1
# Registers : 67
1-bit register : 12
16-bit register : 4
3-bit register : 4
32-bit register : 42
33-bit register : 2
5-bit register : 3
# Multiplexers : 357
1-bit 2-to-1 multiplexer : 197
1-bit 21-to-1 multiplexer : 2
1-bit 24-to-1 multiplexer : 2
1-bit 25-to-1 multiplexer : 2
1-bit 27-to-1 multiplexer : 2
1-bit 28-to-1 multiplexer : 2
1-bit 30-to-1 multiplexer : 2
1-bit 31-to-1 multiplexer : 2
1-bit 32-to-1 multiplexer : 12
16-bit 2-to-1 multiplexer : 19
3-bit 2-to-1 multiplexer : 18
32-bit 2-to-1 multiplexer : 62
32-bit 3-to-1 multiplexer : 1
32-bit 32-to-1 multiplexer : 3
32-bit 4-to-1 multiplexer : 1
33-bit 2-to-1 multiplexer : 30
# Xors : 1
32-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <idTable[31]_dff_34_0> (without init value) has a constant value of 0 in block <uRF>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <exTable[31]_dff_35_0> (without init value) has a constant value of 0 in block <uRF>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <memTable[31]_dff_36_0> (without init value) has a constant value of 0 in block <uRF>. This FF/Latch will be trimmed during the optimization process.
Synthesizing (advanced) Unit <DualPortMemory>.
INFO:Xst:3226 - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DO_B> <DO_A>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 16384-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <CLK> | rise |
| weA | connected to signal <WE_B> | high |
| addrA | connected to signal <Addr_B> | |
| diA | connected to signal <DI_B> | |
| doA | connected to signal <DO_B> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 16384-word x 32-bit | |
| mode | write-first | |
| clkB | connected to signal <CLK> | rise |
| addrB | connected to signal <Addr_A> | |
| doB | connected to signal <DO_A> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <DualPortMemory> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 1
16384x32-bit dual-port block RAM : 1
# Multipliers : 1
33x33-bit multiplier : 1
# Adders/Subtractors : 7
16-bit adder : 3
16-bit subtractor : 1
33-bit adder carry in : 1
6-bit adder : 1
6-bit subtractor : 1
# Registers : 1449
Flip-Flops : 1449
# Multiplexers : 356
1-bit 2-to-1 multiplexer : 197
1-bit 21-to-1 multiplexer : 2
1-bit 24-to-1 multiplexer : 2
1-bit 25-to-1 multiplexer : 2
1-bit 27-to-1 multiplexer : 2
1-bit 28-to-1 multiplexer : 2
1-bit 30-to-1 multiplexer : 2
1-bit 31-to-1 multiplexer : 2
1-bit 32-to-1 multiplexer : 12
16-bit 2-to-1 multiplexer : 19
3-bit 2-to-1 multiplexer : 18
32-bit 2-to-1 multiplexer : 61
32-bit 3-to-1 multiplexer : 1
32-bit 32-to-1 multiplexer : 3
32-bit 4-to-1 multiplexer : 1
33-bit 2-to-1 multiplexer : 30
# Xors : 1
32-bit xor2 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <idTable[31]_dff_34_0> (without init value) has a constant value of 0 in block <register_file>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <exTable[31]_dff_35_0> (without init value) has a constant value of 0 in block <register_file>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <memTable[31]_dff_36_0> (without init value) has a constant value of 0 in block <register_file>. This FF/Latch will be trimmed during the optimization process.
Optimizing unit <SingleCoreProcessor> ...
Optimizing unit <simpleCore> ...
Optimizing unit <decoder> ...
Optimizing unit <register_file> ...
Optimizing unit <branch_control> ...
Optimizing unit <alu> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SingleCoreProcessor, actual ratio is 8.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 1446
Flip-Flops : 1446
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : SingleCoreProcessor.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 2792
# GND : 1
# INV : 14
# LUT1 : 1
# LUT2 : 39
# LUT3 : 108
# LUT4 : 204
# LUT5 : 407
# LUT6 : 1733
# MUXCY : 73
# MUXF7 : 134
# VCC : 1
# XORCY : 77
# FlipFlops/Latches : 1446
# FD : 20
# FDC : 294
# FDCE : 139
# FDCE_1 : 992
# FDP : 1
# RAMS : 16
# RAMB36E1 : 16
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 66
# IBUF : 1
# OBUF : 65
# DSPs : 4
# DSP48E1 : 4
Device utilization summary:
---------------------------
Selected Device : 7k70tfbg676-2
Slice Logic Utilization:
Number of Slice Registers: 1446 out of 82000 1%
Number of Slice LUTs: 2506 out of 41000 6%
Number used as Logic: 2506 out of 41000 6%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 3730
Number with an unused Flip Flop: 2284 out of 3730 61%
Number with an unused LUT: 1224 out of 3730 32%
Number of fully used LUT-FF pairs: 222 out of 3730 5%
Number of unique control sets: 38
IO Utilization:
Number of IOs: 67
Number of bonded IOBs: 67 out of 300 22%
Specific Feature Utilization:
Number of Block RAM/FIFO: 16 out of 135 11%
Number using Block RAM only: 16
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
Number of DSP48E1s: 4 out of 240 1%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 1462 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -2
Minimum period: 13.216ns (Maximum Frequency: 75.666MHz)
Minimum input arrival time before clock: 8.460ns
Maximum output required time after clock: 2.058ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 13.216ns (frequency: 75.666MHz)
Total number of paths / destination ports: 345447289852 / 2614
-------------------------------------------------------------------------
Delay: 6.608ns (Levels of Logic = 13)
Source: Core0/uRF/RegisterTable_26_13 (FF)
Destination: Core0/REG_PC[15]_dff_2_15 (FF)
Source Clock: clk falling
Destination Clock: clk rising
Data Path: Core0/uRF/RegisterTable_26_13 to Core0/REG_PC[15]_dff_2_15
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE_1:C->Q 3 0.240 0.534 Core0/uRF/RegisterTable_26_13 (Core0/uRF/RegisterTable_26_13)
LUT6:I2->O 1 0.043 0.522 Core0/uRF/Mmux_DoutA_813 (Core0/uRF/Mmux_DoutA_813)
LUT6:I2->O 1 0.043 0.000 Core0/uRF/Mmux_DoutA_34 (Core0/uRF/Mmux_DoutA_34)
MUXF7:I1->O 1 0.178 0.350 Core0/uRF/Mmux_DoutA_2_f7_3 (Core0/ID_RegDA<13>)
LUT5:I4->O 1 0.043 0.350 Core0/Mmux_ID_ExOpA_FW103_SW0 (N481)
LUT5:I4->O 2 0.043 0.618 Core0/Mmux_ID_ExOpA_FW103 (Core0/ID_ExOpA_FW<13>)
LUT6:I0->O 4 0.043 0.422 Core0/uBranchCTRL/FlagZ1 (Core0/uBranchCTRL/FlagZ1)
LUT4:I2->O 13 0.043 0.418 Core0/uBranchCTRL/FlagZ7_SW0 (N566)
LUT6:I5->O 17 0.043 0.440 Core0/uBranchCTRL/Mmux_PCIncrement1011 (Core0/uBranchCTRL/Mmux_PCIncrement101)
LUT6:I5->O 1 0.043 0.613 Core0/uBranchCTRL/Mmux_PCIncrement16 (Core0/uBranchCTRL/PCIncrement<1>)
LUT6:I0->O 3 0.043 0.417 Core0/uBranchCTRL/PCIncrement[15]_GND_12_o_equal_16_o<15>1 (Core0/uBranchCTRL/PCIncrement[15]_GND_12_o_equal_16_o<15>)
LUT6:I4->O 12 0.043 0.583 Core0/uBranchCTRL/PCIncrement[15]_GND_12_o_equal_16_o<15>3_1 (Core0/uBranchCTRL/PCIncrement[15]_GND_12_o_equal_16_o<15>3)
LUT6:I2->O 1 0.043 0.405 Core0/Mmux_REG_PC[15]_ID_NextPC[15]_mux_1_OUT71_F (N979)
LUT3:I1->O 1 0.043 0.000 Core0/Mmux_REG_PC[15]_ID_NextPC[15]_mux_1_OUT711 (Core0/REG_PC[15]_ID_NextPC[15]_mux_1_OUT<15>)
FDC:D -0.000 Core0/REG_PC[15]_dff_2_15
----------------------------------------
Total 6.608ns (0.934ns logic, 5.674ns route)
(14.1% logic, 85.9% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 10582264 / 1654
-------------------------------------------------------------------------
Offset: 8.460ns (Levels of Logic = 17)
Source: reset (PAD)
Destination: Core0/REG_PC[15]_dff_2_15 (FF)
Destination Clock: clk rising
Data Path: reset to Core0/REG_PC[15]_dff_2_15
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1681 0.000 0.783 reset_IBUF (reset_IBUF)
LUT4:I0->O 248 0.043 0.783 Core0/Mmux_ID_I91 (Core0/ID_I<17>)
LUT6:I0->O 1 0.043 0.522 Core0/uRF/Mmux_FW_exTable_A_81 (Core0/uRF/Mmux_FW_exTable_A_81)
LUT6:I2->O 1 0.043 0.000 Core0/uRF/Mmux_FW_exTable_A_3 (Core0/uRF/Mmux_FW_exTable_A_3)
MUXF7:I1->O 77 0.178 0.633 Core0/uRF/Mmux_FW_exTable_A_2_f7 (Core0/extable_a)
LUT4:I1->O 2 0.043 0.527 Core0/Mmux_ID_ExOpA_FW241 (Core0/Mmux_ID_ExOpA_FW24)
LUT4:I0->O 2 0.043 0.608 Core0/Mmux_ID_ExOpA_FW243_SW1 (N377)
LUT6:I1->O 1 0.043 0.000 Core0/Mmux_ID_ExOpA_FW343_SW0_F (N1025)
MUXF7:I0->O 1 0.176 0.350 Core0/Mmux_ID_ExOpA_FW343_SW0 (N379)
LUT6:I5->O 1 0.043 0.350 Core0/uBranchCTRL/FlagZ3 (Core0/uBranchCTRL/FlagZ3)
LUT6:I5->O 16 0.043 0.488 Core0/uBranchCTRL/FlagZ4 (Core0/uBranchCTRL/FlagZ4)
LUT6:I4->O 17 0.043 0.440 Core0/uBranchCTRL/Mmux_PCIncrement1011 (Core0/uBranchCTRL/Mmux_PCIncrement101)
LUT6:I5->O 1 0.043 0.613 Core0/uBranchCTRL/Mmux_PCIncrement16 (Core0/uBranchCTRL/PCIncrement<1>)
LUT6:I0->O 3 0.043 0.417 Core0/uBranchCTRL/PCIncrement[15]_GND_12_o_equal_16_o<15>1 (Core0/uBranchCTRL/PCIncrement[15]_GND_12_o_equal_16_o<15>)
LUT6:I4->O 12 0.043 0.583 Core0/uBranchCTRL/PCIncrement[15]_GND_12_o_equal_16_o<15>3_1 (Core0/uBranchCTRL/PCIncrement[15]_GND_12_o_equal_16_o<15>3)
LUT6:I2->O 1 0.043 0.405 Core0/Mmux_REG_PC[15]_ID_NextPC[15]_mux_1_OUT71_F (N979)
LUT3:I1->O 1 0.043 0.000 Core0/Mmux_REG_PC[15]_ID_NextPC[15]_mux_1_OUT711 (Core0/REG_PC[15]_ID_NextPC[15]_mux_1_OUT<15>)
FDC:D -0.000 Core0/REG_PC[15]_dff_2_15
----------------------------------------
Total 8.460ns (0.956ns logic, 7.504ns route)
(11.3% logic, 88.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 505 / 65
-------------------------------------------------------------------------
Offset: 2.058ns (Levels of Logic = 3)
Source: Core0/WB_MemCTRL[2]_dff_74_0 (FF)
Destination: MemWData<31> (PAD)
Source Clock: clk rising
Data Path: Core0/WB_MemCTRL[2]_dff_74_0 to MemWData<31>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 70 0.236 0.740 Core0/WB_MemCTRL[2]_dff_74_0 (Core0/WB_MemCTRL[2]_dff_74_0)
LUT5:I0->O 8 0.043 0.652 Core0/Mmux_MemWriteData3421 (Core0/Mmux_MemWriteData342)
LUT6:I0->O 2 0.043 0.344 Core0/Mmux_MemWriteData50 (MemWData_31_OBUF)
OBUF:I->O 0.000 MemWData_31_OBUF (MemWData<31>)
----------------------------------------
Total 2.058ns (0.322ns logic, 1.736ns route)
(15.6% logic, 84.4% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 12.194| 6.608| 2.249| |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 43.00 secs
Total CPU time to Xst completion: 34.91 secs
-->
Total memory usage is 528584 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 11 ( 0 filtered)
Number of infos : 1 ( 0 filtered)