🐞 Bug: Spacing error in the Boolean Logic Table

[Asrani-Aman]

Is there an existing issue for this?

• I have searched the existing issues

Describe the bug

When we create a circuit using combinational Analysis tool, i.e. by using the boolean logic table , then we can see that the padding in the boolean table is not equal from side . here is the image and video that show the bug.

WhatsApp.Video.2024-02-08.at.11.53.03.mp4

Steps To Reproduce

1. Go to Simulator
2. Click on tools
3. click on Combinational Analysis
4. enter either input, output or boolean logic function
5. you can see the indentations padding error in the boolean logic table

Expected Behavior

The padding / indentations should be equal from all side .

Screenshots

No response

Device Information [optional]

- OS: macos
- Browser: chrome
- version:

Additional context

No response

Are you working on this issue?

Yes

[tanmoysrt]

Hi @Asrani-Aman you can raise the PR