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Register Stacks
Xita's core internal structure for CPU register management is known as a Register Stack. Register stacks allow the system to arbitrarily and randomly purpose CPU registers for each function.
Each AArch64 stack is 26 wide and includes registers X0 -- X30 for general integer computations. X14-16 are used as control registers, with X16 used as Xita's Serialization Register on ARM chips.
Register stacks can be randomized in two ways:
- Static Randomization - Register stacks are randomized at build-time
- Dynamic Randomization - Register stacks are randomized at run-time
A completely new register stack is allocated and created for each function. The order of each register stack is arbitrary and randomized for each function. In other words, two functions that are identical in functionality would have two separate, unique register stack orders. The order of the register stack is internally managed and is never transparent to the userspace.
If functions are dynamically randomized, register stacks' orders are not exposed within bytecode; this has a profound implication on a module's efficiency. On the other hand, if functions are statically randomized, the register stacks' orders are exposed within bytecode, but the module will execute much faster.
Throughout this GitHub project space, you will see the phrase "Decode n parameters". There are times when the Xita backend needs to store metadata about the instantaneous register stack -- this is done using the system's Serialization Register.
To "Decode 1 parameter" means to compare the value in the serialization register (x16) against the Xita Register Table (See Below). For example: if the decoded value of x16 is equal to 5, the data for the function call can be found in AArch64 register x4.
If more than one parameter needs to be decoded, they are serialized into x16 according to the following pseudo code:
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x16is set to the value of the first parameter's ADR code (e.g. 5 ==x4) - The second parameter's ADR code is shifted 5 bits and added to
x16 - the nth parameter's ADR code is shifted (5*(n-1)) bits and added to
x16- NOTE: 64-bit registers can only serialize 12 ADR codes at a time, so it may be necessary to use XCR1-XCR3 in special cases.
| ARM Register | Xita Name | Purpose |
|---|---|---|
| x0 | ADR1 | Holds Arbitrary Data/Pointer (#1) |
| x1 | ADR2 | Holds Arbitrary Data/Pointer (#2) |
| x2 | ADR3 | Holds Arbitrary Data/Pointer (#3) |
| x3 | ADR4 | Holds Arbitrary Data/Pointer (#4) |
| x4 | ADR5 | Holds Arbitrary Data/Pointer (#5) |
| x5 | ADR6 | Holds Arbitrary Data/Pointer (#6) |
| x6 | ADR7 | Holds Arbitrary Data/Pointer (#7) |
| x7 | ADR8 | Holds Arbitrary Data/Pointer (#8) |
| x8 | ADR9 | Holds Arbitrary Data/Pointer (#9) |
| x9 | ADR10 | Holds Arbitrary Data/Pointer (#10) |
| x10 | ADR11 | Holds Arbitrary Data/Pointer (#11) |
| x11 | ADR12 | Holds Arbitrary Data/Pointer (#12) |
| x12 | ADR13 | Holds Arbitrary Data/Pointer (#13) |
| x13 | XCR1 | Xita Control Register (#1) |
| x14 | XCR2 | Xita Control Register (#2) |
| x15 | XCR3 | Xita Control Register (#3) |
| x16 | XSR | Xita Serialization Register |
| X17 | ADR14 | Holds Arbitrary Data/Pointer (#14) |
| x18 | ADR15 | Holds Arbitrary Data/Pointer (#15) |
| x19 | ADR16 | Holds Arbitrary Data/Pointer (#16) |
| X20 | ADR17 | Holds Arbitrary Data/Pointer (#17) |
| x21 | ADR18 | Holds Arbitrary Data/Pointer (#18) |
| x22 | ADR19 | Holds Arbitrary Data/Pointer (#19) |
| x23 | ADR20 | Holds Arbitrary Data/Pointer (#20) |
| x24 | ADR21 | Holds Arbitrary Data/Pointer (#21) |
| x25 | ADR22 | Holds Arbitrary Data/Pointer (#22) |
| x26 | ADR23 | Holds Arbitrary Data/Pointer (#23) |
| x27 | ADR24 | Holds Arbitrary Data/Pointer (#24) |
| x28 | ADR25 | Holds Arbitrary Data/Pointer (#25) |
| x29 | ADR26 | Holds Arbitrary Data/Pointer (#26) |
| x30 | ADR27 | Holds Arbitrary Data/Pointer (#27) |
| ARM Register | Xita Name | Purpose |
|---|---|---|
| r0 | - | RESERVED |
| r1 | ADR1 | Holds Arbitrary Data/Pointer (#1) |
| r2 | ADR2 | Holds Arbitrary Data/Pointer (#2) |
| r3 | ADR3 | Holds Arbitrary Data/Pointer (#3) |
| r4 | ADR4 | Holds Arbitrary Data/Pointer (#4) |
| r5 | ADR5 | Holds Arbitrary Data/Pointer (#5) |
| r6 | ADR6 | Holds Arbitrary Data/Pointer (#6) |
| r7 | ADR7 | Holds Arbitrary Data/Pointer (#7) |
| r8 | ADR8 | Holds Arbitrary Data/Pointer (#8) |
| r9 | ADR9 | Holds Arbitrary Data/Pointer (#9) |
| r10 | ADR10 | Holds Arbitrary Data/Pointer (#10) |
| r11 | ADR11 | Holds Arbitrary Data/Pointer (#11) |
| r12 | XSR | Xita Serialization Register |
| r13 | SP | Stack Pointer (ARMv7 Core) |
| r14 | LR | Link Register (ARMv7 Core) |
| r15 | PC | Instruction Pointer (ARMv7 Core) |
| x86 Register | Xita Name | Purpose |
|---|---|---|
| rax | XSR | Xita Serialization Register |
| rbx | ADR1 | Holds Arbitrary Data/Pointer (#1) |
| rcx | ADR2 | Holds Arbitrary Data/Pointer (#2) |
| rdx | ADR3 | Holds Arbitrary Data/Pointer (#3) |
| rdi | - | RESERVED |
| rsi | ADR4 | Holds Arbitrary Data/Pointer (#4) |
| rdi | ADR5 | Holds Arbitrary Data/Pointer (#5) |
| r8 | BP | Base Address (Bottom of Stack) |
| r9 | SP | Stack Pointer (Top of Stack) |
| r10 | IP | Instruction Pointer |
| r11 | ADR6 | Holds Arbitrary Data/Pointer (#6) |
| r12 | ADR7 | Holds Arbitrary Data/Pointer (#7) |
| r13 | ADR8 | Holds Arbitrary Data/Pointer (#8) |
| r14 | ADR9 | Holds Arbitrary Data/Pointer (#9) |
| r15 | ADR10 | Holds Arbitrary Data/Pointer (#10) |
**IMPORTANT NOTE: ** Codeus Tech will never provide support for x86 (32-bit) architecture, because there is very little advantage over Linux to leverage in development. Although it allows the secure kernel to run on x86 chips, it will almost certainly be much slower in execution than systems like Tails, Qubes, etc.
If it was ever to be supported on x86, it would follow the following scheme.
| x86 Register | Xita Name | Purpose |
|---|---|---|
| eax | ADR1 | Holds Arbitrary Data/Pointer (#1) |
| ebx | ADR2 | Holds Arbitrary Data/Pointer (#2) |
| ecx | ADR3 | Holds Arbitrary Data/Pointer (#3) |
| edx | ADR4 | Holds Arbitrary Data/Pointer (#4) |
| cs | CS | Code Segment Register |
| ds | DS | Data Segment Register |
| es | XSR | Xita Serialization Register |
| fs | XCR1 | Xita Control Register (16-bit) |
| gs | XCR2 | Xita Control Register (16-bit) |
| ss | SS | Stack Segment Register |
| esi | ADR5 | Holds Arbitrary Data/Pointer (#5) |
| edi | ADR6 | Holds Arbitrary Data/Pointer (#6) |
| ebp | BP | Base Address (Bottom of Stack) |
| esp | SP | Stack Pointer (Top of Stack) |
| eip | IP | Instruction Pointer |
| eflags | PC | x86 Runtime "Flags" Register |