Reaction Timer State Machine

Electronic devices operate at remarkably fast speeds, with the typical delay through a logic gate being less than 1 ns. This project aims to use a logic circuit to measure the speed of a much slower type of device—a person. A circuit will be designed and coded to measure the reaction time of a person to a specific event. This reaction timer will be implemented on the MAX 10 (10M50DAF484C7G) Field Programmable Gate Array (FPGA) utilizing Verilog Hardware Description Language (VHDL) and Quartus Prime. The circuit will illuminate an LED on the Terasic DE10-LITE board a random amount of time after a “start” button is pushed and released. The goal is for the player to switch on the “stop” switch that corresponds to a randomly lit LED as quickly as possible. The reaction time will be displayed in milliseconds on the board’s seven-segment display after the “stop” switch is turned on. Furthermore, if the start or stop inputs triggered before the LED is lit, then the random timer is stopped, and everything is reset. An asynchronous reset switch will also reset the game to display the latest high score.