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When building an FPGA image the tool analyzes verilog modules to determine if build depends on them,
A module can be declared with the beginning parenthesis on the first line:
module verilog_module (
or with the parenthesis on the second line
The system is not recognizing the second version
The text was updated successfully, but these errors were encountered:
generate statements confuse the verilog parser
Sorry, something went wrong.
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When building an FPGA image the tool analyzes verilog modules to determine if build depends on them,
A module can be declared with the beginning parenthesis on the first line:
module verilog_module (
or with the parenthesis on the second line
module verilog_module
(
The system is not recognizing the second version
The text was updated successfully, but these errors were encountered: