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Add atomicFence() function to core.atomic.
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alexrp authored and alexrp committed Jul 4, 2012
1 parent 5b4a78c commit 07eddbd
Showing 1 changed file with 57 additions and 0 deletions.
57 changes: 57 additions & 0 deletions src/core/atomic.d
Expand Up @@ -49,6 +49,8 @@ version( AsmX86 )
{
return addr % T.sizeof == 0;
}

import core.cpuid; // For SSE detection for fence instructions.
}


Expand Down Expand Up @@ -137,6 +139,15 @@ version( CoreDdoc )
rel, /// sink-load + sink-store barrier
seq, /// fully sequenced (acq + rel)
}

/**
* Inserts a full load/store memory fence (on platforms that need it). This ensures
* that all loads and stores before a call to this function are executed before any
* loads and stores after the call.
*/
void atomicFence() nothrow
{
}
}
else version( AsmX86_32 )
{
Expand Down Expand Up @@ -573,6 +584,29 @@ else version( AsmX86_32 )
static assert( false, "Invalid template type specified." );
}
}


void atomicFence() nothrow
{
if (sse2)
{
asm
{
mfence;
}
}
else
{
// The cpuid instruction serializes, but is not ideal
// for this (since it's relatively slow), hence why
// we prefer the SSE2 mfence instruction.
asm
{
mov EAX, 0;
cpuid;
}
}
}
}
else version( AsmX86_64 )
{
Expand Down Expand Up @@ -1009,6 +1043,29 @@ else version( AsmX86_64 )
static assert( false, "Invalid template type specified." );
}
}


void atomicFence() nothrow
{
if (sse2)
{
asm
{
mfence;
}
}
else
{
// The cpuid instruction serializes, but is not ideal
// for this (since it's relatively slow), hence why
// we prefer the SSE2 mfence instruction.
asm
{
mov EAX, 0;
cpuid;
}
}
}
}

// This is an ABI adapter that works on all architectures. It type puns
Expand Down

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