Skip to content
This repository has been archived by the owner on Oct 12, 2022. It is now read-only.

attributes for inline asm #975

Merged
merged 1 commit into from Oct 10, 2014
Merged

attributes for inline asm #975

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
104 changes: 52 additions & 52 deletions src/core/atomic.d
View file
Open in desktop

Large diffs are not rendered by default.

8 changes: 4 additions & 4 deletions src/core/bitop.d
View file
Open in desktop
Expand Up @@ -319,17 +319,17 @@ unittest
{
version (AsmX86)
{
asm { naked; }
asm pure nothrow @nogc { naked; }

version (D_InlineAsm_X86_64)
{
version (Win64)
asm { mov EAX, ECX; }
asm pure nothrow @nogc { mov EAX, ECX; }
else
asm { mov EAX, EDI; }
asm pure nothrow @nogc { mov EAX, EDI; }
}

asm
asm pure nothrow @nogc
{
// Author: Tiago Gasiba.
mov EDX, EAX;
Expand Down
34 changes: 17 additions & 17 deletions src/core/cpuid.d
View file
Open in desktop
Expand Up @@ -436,7 +436,7 @@ void getcacheinfoCPUID2()
// for old single-core CPUs.
uint numinfos = 1;
do {
asm {
asm pure nothrow @nogc {
mov EAX, 2;
cpuid;
mov a, EAX;
Expand Down Expand Up @@ -478,7 +478,7 @@ void getcacheinfoCPUID4()
int cachenum = 0;
for(;;) {
uint a, b, number_of_sets;
asm {
asm pure nothrow @nogc {
mov EAX, 4;
mov ECX, cachenum;
cpuid;
Expand Down Expand Up @@ -516,7 +516,7 @@ void getcacheinfoCPUID4()
void getAMDcacheinfo()
{
uint c5, c6, d6;
asm {
asm pure nothrow @nogc {
mov EAX, 0x8000_0005; // L1 cache
cpuid;
// EAX has L1_TLB_4M.
Expand All @@ -533,15 +533,15 @@ void getAMDcacheinfo()
// AMD K6-III or K6-2+ or later.
ubyte numcores = 1;
if (max_extended_cpuid >=0x8000_0008) {
asm {
asm pure nothrow @nogc {
mov EAX, 0x8000_0008;
cpuid;
mov numcores, CL;
}
++numcores;
if (numcores>maxCores) maxCores = numcores;
}
asm {
asm pure nothrow @nogc {
mov EAX, 0x8000_0006; // L2/L3 cache
cpuid;
mov c6, ECX; // L2 cache info
Expand All @@ -568,7 +568,7 @@ void getCpuInfo0B()
int threadsPerCore;
uint a, b, c, d;
do {
asm {
asm pure nothrow @nogc {
mov EAX, 0x0B;
mov ECX, level;
cpuid;
Expand Down Expand Up @@ -599,7 +599,7 @@ void cpuidX86()
uint a, b, c, d, a2;
version(D_InlineAsm_X86)
{
asm {
asm pure nothrow @nogc {
mov EAX, 0;
cpuid;
mov a, EAX;
Expand All @@ -611,7 +611,7 @@ void cpuidX86()
}
else version(D_InlineAsm_X86_64)
{
asm {
asm pure nothrow @nogc {
mov EAX, 0;
cpuid;
mov a, EAX;
Expand All @@ -621,7 +621,7 @@ void cpuidX86()
mov [RAX + 8], ECX;
}
}
asm {
asm pure nothrow @nogc {
mov EAX, 0x8000_0000;
cpuid;
mov a2, EAX;
Expand All @@ -633,7 +633,7 @@ void cpuidX86()
probablyIntel = vendorID == "GenuineIntel";
probablyAMD = vendorID == "AuthenticAMD";
uint apic = 0; // brand index, apic id
asm {
asm pure nothrow @nogc {
mov EAX, 1; // model, stepping
cpuid;
mov a, EAX;
Expand All @@ -648,7 +648,7 @@ void cpuidX86()
{
uint ext;

asm
asm pure nothrow @nogc
{
mov EAX, 7; // Structured extended feature leaf.
mov ECX, 0; // Main leaf.
Expand All @@ -661,7 +661,7 @@ void cpuidX86()

if (miscfeatures & OSXSAVE_BIT)
{
asm {
asm pure nothrow @nogc {
mov ECX, 0;
xgetbv;
mov d, EDX;
Expand All @@ -672,7 +672,7 @@ void cpuidX86()
amdfeatures = 0;
amdmiscfeatures = 0;
if (max_extended_cpuid >= 0x8000_0001) {
asm {
asm pure nothrow @nogc {
mov EAX, 0x8000_0001;
cpuid;
mov c, ECX;
Expand All @@ -693,7 +693,7 @@ void cpuidX86()

if (!probablyIntel && max_extended_cpuid >= 0x8000_0008) {
// determine max number of cores for AMD
asm {
asm pure nothrow @nogc {
mov EAX, 0x8000_0008;
cpuid;
mov c, ECX;
Expand All @@ -714,7 +714,7 @@ void cpuidX86()
char *procptr = processorNameBuffer.ptr;
version(D_InlineAsm_X86)
{
asm {
asm pure nothrow @nogc {
push ESI;
mov ESI, procptr;
mov EAX, 0x8000_0002;
Expand All @@ -740,7 +740,7 @@ void cpuidX86()
}
else version(D_InlineAsm_X86_64)
{
asm {
asm pure nothrow @nogc {
push RSI;
mov RSI, procptr;
mov EAX, 0x8000_0002;
Expand Down Expand Up @@ -846,7 +846,7 @@ bool hasCPUID()
else
{
uint flags;
asm {
asm nothrow @nogc {
pushfd;
pop EAX;
mov flags, EAX;
Expand Down
4 changes: 2 additions & 2 deletions src/core/stdc/stdio.d
View file
Open in desktop
Expand Up @@ -856,7 +856,7 @@ version(CRuntime_DigitalMars)
// this is copied from semlock.h in DMC's runtime.
private void LockSemaphore(uint num)
{
asm
asm nothrow @nogc
{
mov EDX, num;
lock;
Expand All @@ -873,7 +873,7 @@ version(CRuntime_DigitalMars)
// this is copied from semlock.h in DMC's runtime.
private void UnlockSemaphore(uint num)
{
asm
asm nothrow @nogc
{
mov EDX, num;
lock;
Expand Down
2 changes: 1 addition & 1 deletion src/core/sys/windows/dll.d
View file
Open in desktop
Expand Up @@ -327,7 +327,7 @@ public:
return true;

void** peb;
asm
asm pure nothrow @nogc
{
mov EAX,FS:[0x30];
mov peb, EAX;
Expand Down
5 changes: 2 additions & 3 deletions src/core/sys/windows/threadaux.d
View file
Open in desktop
Expand Up @@ -163,7 +163,7 @@ private:
{
version(Win32)
{
asm
asm pure nothrow @nogc
{
naked;
mov EAX,FS:[0x18];
Expand All @@ -172,7 +172,7 @@ private:
}
else version(Win64)
{
asm
asm pure nothrow @nogc
{
naked;
mov RAX,0x30;
Expand Down Expand Up @@ -333,4 +333,3 @@ public:
thread_aux.impersonate_thread(id, &rt_moduleTlsDtor);
}
}

44 changes: 22 additions & 22 deletions src/core/thread.d
View file
Open in desktop
Expand Up @@ -210,7 +210,7 @@ version( Windows )

version( D_InlineAsm_X86 )
{
asm { fninit; }
asm nothrow @nogc { fninit; }
}

try
Expand Down Expand Up @@ -2278,7 +2278,7 @@ else
else version (AsmX86_Posix)
{
size_t[3] regs = void;
asm
asm pure nothrow @nogc
{
mov [regs + 0 * 4], EBX;
mov [regs + 1 * 4], ESI;
Expand All @@ -2290,7 +2290,7 @@ else
else version (AsmX86_Windows)
{
size_t[3] regs = void;
asm
asm pure nothrow @nogc
{
mov [regs + 0 * 4], EBX;
mov [regs + 1 * 4], ESI;
Expand All @@ -2302,7 +2302,7 @@ else
else version (AsmX86_64_Posix)
{
size_t[5] regs = void;
asm
asm pure nothrow @nogc
{
mov [regs + 0 * 8], RBX;
mov [regs + 1 * 8], R12;
Expand All @@ -2316,7 +2316,7 @@ else
else version (AsmX86_64_Windows)
{
size_t[7] regs = void;
asm
asm pure nothrow @nogc
{
mov [regs + 0 * 8], RBX;
mov [regs + 1 * 8], RSI;
Expand Down Expand Up @@ -3032,9 +3032,9 @@ nothrow:
private void* getStackTop() nothrow
{
version (D_InlineAsm_X86)
asm { naked; mov EAX, ESP; ret; }
asm pure nothrow @nogc { naked; mov EAX, ESP; ret; }
else version (D_InlineAsm_X86_64)
asm { naked; mov RAX, RSP; ret; }
asm pure nothrow @nogc { naked; mov RAX, RSP; ret; }
else version (GNU)
return __builtin_frame_address(0);
else
Expand All @@ -3047,9 +3047,9 @@ private void* getStackBottom() nothrow
version (Windows)
{
version (D_InlineAsm_X86)
asm { naked; mov EAX, FS:4; ret; }
asm pure nothrow @nogc { naked; mov EAX, FS:4; ret; }
else version(D_InlineAsm_X86_64)
asm
asm pure nothrow @nogc
{ naked;
mov RAX, 8;
mov RAX, GS:[RAX];
Expand Down Expand Up @@ -3461,7 +3461,7 @@ private

version( AsmX86_Windows )
{
asm
asm pure nothrow @nogc
{
naked;

Expand Down Expand Up @@ -3499,7 +3499,7 @@ private
}
else version( AsmX86_64_Windows )
{
asm
asm pure nothrow @nogc
{
naked;

Expand Down Expand Up @@ -3567,7 +3567,7 @@ private
}
else version( AsmX86_Posix )
{
asm
asm pure nothrow @nogc
{
naked;

Expand Down Expand Up @@ -3599,7 +3599,7 @@ private
}
else version( AsmX86_64_Posix )
{
asm
asm pure nothrow @nogc
{
naked;

Expand Down Expand Up @@ -4447,7 +4447,7 @@ private:
{
static EXCEPTION_REGISTRATION* fs0()
{
asm
asm pure nothrow @nogc
{
naked;
mov EAX, FS:[0];
Expand Down Expand Up @@ -4486,7 +4486,7 @@ private:
// to 16 bytes.
static void trampoline()
{
asm
asm pure nothrow @nogc
{
naked;
sub RSP, 32; // Shadow space (Win64 calling convention)
Expand Down Expand Up @@ -5073,27 +5073,27 @@ version( AsmX86_64_Windows )
void testNonvolatileRegister(alias REG)()
{
auto zeroRegister = new Fiber(() {
mixin("asm { xor "~REG~", "~REG~"; }");
mixin("asm pure nothrow @nogc { xor "~REG~", "~REG~"; }");
});
long after;

mixin("asm { mov "~REG~", 0xFFFFFFFFFFFFFFFF; }");
mixin("asm pure nothrow @nogc { mov "~REG~", 0xFFFFFFFFFFFFFFFF; }");
zeroRegister.call();
mixin("asm { mov after, "~REG~"; }");
mixin("asm pure nothrow @nogc { mov after, "~REG~"; }");

assert(after == -1);
}

void testNonvolatileRegisterSSE(alias REG)()
{
auto zeroRegister = new Fiber(() {
mixin("asm { xorpd "~REG~", "~REG~"; }");
mixin("asm pure nothrow @nogc { xorpd "~REG~", "~REG~"; }");
});
long[2] before = [0xFFFFFFFF_FFFFFFFF, 0xFFFFFFFF_FFFFFFFF], after;

mixin("asm { movdqu "~REG~", before; }");
mixin("asm pure nothrow @nogc { movdqu "~REG~", before; }");
zeroRegister.call();
mixin("asm { movdqu after, "~REG~"; }");
mixin("asm pure nothrow @nogc { movdqu after, "~REG~"; }");

assert(before == after);
}
Expand Down Expand Up @@ -5127,7 +5127,7 @@ version( D_InlineAsm_X86_64 )
void testStackAlignment()
{
void* pRSP;
asm
asm pure nothrow @nogc
{
mov pRSP, RSP;
}
Expand Down