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Generate timing diagram #27

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DrSensor opened this issue Jul 6, 2019 · 1 comment
Open

Generate timing diagram #27

DrSensor opened this issue Jul 6, 2019 · 1 comment
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enhancement New feature or request
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@DrSensor
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DrSensor commented Jul 6, 2019

How it looks like? (maybe)

entry |> State1 |> exit

state State2 {
  State21 >< activity

  initial -> State21
  State21 -> State22 @ Event
}

initial -> State1
State1 -> State2 @ Event[guard] |> action
State2 -> State1 @ Reset |> action

From 馃憜 to 馃憞
Screenshot_20190706_065814

{signal: [
  {name: 'execution', wave: '03524.02350', data: ['entry', 'exit', 'action', 'activity', 'action', 'entry', 'exit']},
  {name: 'trigger',   wave: '0..=0.==0..', data: ['Event [<i>guard</i>]', 'Event', 'Reset']},

  {name: 'State1',    wave: '01.x...1..0'},
  ['State2',
   {name: 'State21',  wave: '0x.1..x...0'},
   {name: 'State22',  wave: '0x....1x..0'},
  ],
],
  config: { hscale: 3 }
}

Paste 馃憜 to https://wavedrom.com/editor.html

I think I should move action, entry, and exit inside state timeline 馃. Also separate activity to different lifeline, especially when in the compound state.

However, for easier implementation, it should lay flat. Imagine having an action that executed many times, how long the data will be 馃槄

Something needs to watch out!

  • waveform doesn't automatically fit the diagram with the texts
  • probably there will be a need for sorting (I hope not because I use wave: 0.x..0) if I want to support Arrows Splines
  • activity inside Compound State could be tricky to visualize. Maybe activity should be separated as a different lifeline
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Other approachs
  • transpile into LLHD then visualize using gtkwave or alike
  • generate VCD file
@DrSensor DrSensor added the enhancement New feature or request label Jul 6, 2019
@DrSensor DrSensor added this to the v2.0-dev milestone Jul 6, 2019
@brucou
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brucou commented Jul 22, 2019

My background is electrical engineering so it might get influence from that. There are several way to analyze FSM in ASIC design (see [here](FSM-viz Verilog)). Let's move the discussion in #27.

Yeah I had a look at the link. It is true that chips are on a clock, so it makes sense to visualize it that way. Did you ever heard about Lucid Synchrone or Esterel? Those are synchronous languages compiling to fsm with model checking and all the jazz. They embed a notion of clock and use clocked streams for everything.

For the FSM I deal with, I think the interesting information for tracing is the sequence itself , i.e. instead of visualizing [(x_i, t_i] i.e. a sequence of x occurring at time t it is more interesting to visualize just the [x_i] directly on the graph visualization. But I haven't given too much thoughts to that.

@DrSensor DrSensor added this to In progress in Collaboration Jul 27, 2019
@DrSensor DrSensor moved this from In progress to To do in Collaboration Jul 27, 2019
@DrSensor DrSensor moved this from To do to Discussing in Collaboration Jul 27, 2019
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