My notes while coding this code (i writed this while plaining to code)

[Duiccni]

'nop'				:	90
No operation
'hlt'				:	F4
Enter Halt state
'clc'				: 	F8
Clear Carry Flag
'cmc'				: 	F5
Complement Carry Flag
'cld'				: 	FC
Clear Direction Flag
'cli'				: 	FA
Clear Interrupt Flag


r/m:
ax, 0
cx, 1
dx, 2
bx, 3
sp, 4
bp, 5
si, 6
di, 7


# # # area only for 'jmp' instruction # # #
'jmp rel8'			:			EB <rel8>
'jmp rel16'			:			E9 <rel16>
'jmp rel32'			:	<32bc>	E9 <rel32>
jmp <rel> -> RIP += <rel>
rel == signed intager

for absoulte address:
'jmp <dest>':
rel = <dest> - RIP
RIP += <dest> - RIP
RIP = <dest>


r/m: (e0 + index)
ax = e0
cx = e1
dx = e2
bx = e3
sp = e4
bp = e5
si = e6
di = e7

pointer:
'jmp r/m16'			:			FF <r/m16>
'jmp r/m32'			:	<32bc>	FF <r/m32>
jmp <r/m> -> RIP = <r/m>
r/m == general purpose registers
# # # - - - - - - - - - - - - # # #

# # # area only for 'neg' instruction # # #
r/m: 16-32 bit	-> (d8 + index)
	 8 bit		-> (dc + index) or (d8 + 4 + index)
low:
al, ax, eax	= d8
cl, cx, ecx	= d9
dl, dx, edx	= da
bl, bx, ebx	= db
sp, esp		= dc
bp, ebp		= dd
si, esi		= de
di, edi		= df

high:
ah 			= dc
ch 			= dd
dh 			= de
bh 			= df

'neg r/m8'			 :			f6 <r/m8>
'neg r/m16'			 :			f7 <r/m16>
'neg r/m32'			 :	<32bc>	f7 <r/m32>

pointer symbol for neg = 0x1e
'neg <size8>  [m16]' :			f6 1e <m16l> <m16h>
'neg <size16> [m16]' :			f7 1e <m16l> <m16h>
'neg <size32> [m16]' :	<32bc>	f7 1e <m16l> <m16h>
r/m = not->r/m + 1
# # # - - - - - - - - - - - - # # #

# # # area only for 'not' instruction # # #
r/m: 16-32 bit	-> (d0 + index)
	 8 bit		-> (d4 + index) or (d0 + 4 + index)
low:
al, ax, eax	= d0
cl, cx, ecx	= d1
dl, dx, edx	= d2
bl, bx, ebx	= d3
sp, esp		= d4
bp, ebp		= d5
si, esi		= d6
di, edi		= d7

high:
ah 			= d4
ch 			= d5
dh 			= d6
bh 			= d7

'not r/m8'			:			f6    <r/m8>
'not r/m16'			:			f7    <r/m16>
'not r/m32'			:	<32bc>	f7 	  <r/m32>

pointer symbol for not = 0x16
'not <size8>  [m16]' :			f6 16 <m16l> <m16h>
'not <size16> [m16]' :			f7 16 <m16l> <m16h>
'not <size32> [m16]' :	<32bc>	f7 16 <m16l> <m16h>
r/m = not->r/m
# # # - - - - - - - - - - - - # # #

# # # area only for 'inc' instruction # # #
r/m: 16-32 bit	-> (40 + index)
	 8 bit		-> (c0 + index8)

reg8:
al 			= 0xc0
cl 			= 0xc1
dl 			= 0xc2
bl 			= 0xc3

ah 			= 0xc4
ch 			= 0xc5
dh 			= 0xc6
bh 			= 0xc7

'inc reg8'			:			fe    <reg8>

'inc reg16'			: 			(40 + reg16[i])
'inc reg32'			:	<32bc>	(40 + reg16[i])

pointer symbol for inc = 0x06
'inc <size8>  [m16]' :			fe 06 <m16l> <m16h>
'inc <size16> [m16]' :			ff 06 <m16l> <m16h>
'inc <size32> [m16]' :	<32bc>	ff 06 <m16l> <m16h>
r/m += 1
r/m =  r/m + 1
# # # - - - - - - - - - - - - # # #

# # # area only for 'dec' instruction # # #
r/m: 16-32 bit	-> (48 + index)
	 8 bit		-> (c8 + index8)

reg8:
al 			= 0xc8
cl 			= 0xc9
dl 			= 0xca
bl 			= 0xcb

ah 			= 0xcc
ch 			= 0xcd
dh 			= 0xce
bh 			= 0xcf

'dec reg8'			:			fe    <reg8>

'dec reg16'			: 			(48 + reg16[i])
'dec reg32'			:	<32bc>	(48 + reg16[i])

pointer symbol for dec = 0x0e
'dec <size8>  [m16]' :			fe 0e <m16l> <m16h>
'dec <size16> [m16]' :			ff 0e <m16l> <m16h>
'dec <size32> [m16]' :	<32bc>	ff 0e <m16l> <m16h>
r/m += 1
r/m =  r/m + 1
# # # - - - - - - - - - - - - # # #

# # # # area only for 'MOV' instruction # # # #
index:
al, cl, dl, bl (0 - 3)				# low
ah, ch, dh, bh (4 - 7)				# high
ax, cx, dx, bx (8 - 11[0xb])		# low
sp, bp, si, di (12[0xc] - 15[0xf])  # low
NOTE: 32 bit registers same with 16 bit ones with <32bc> indicator

***use <32bc> only on need***
'mov reg(any_size), <byte>		:  <32bc>	(b0 + index) <m(s0)> <m(s1)> <m(s2)> <m(s3)>


'mov al, 	[m16]'				: 			a0 <m16l> <m16h>
'mov ax, 	[m16]'				: 			a1 <m16l> <m16h>
'mov eax, 	[m16]'				:  <32bc>	a1 <m16l> <m16h>

'mov [m16], 	al'				: 			a2 <m16l> <m16h>
'mov [m16], 	ax'				: 			a3 <m16l> <m16h>
'mov [m16], 	eax'			:  <32bc>	a3 <m16l> <m16h>

<reg_code>: xy -> x ?= (0-3) & y-> (6 or 0xE)
ah 			= 26
ch 			= 2E  # only 8 bit
dh 			= 36
bh 			= 3E

cl, cx, ecx	= 0E 2 = 14 8x - 2
dl, dx, edx	= 16 3 = 22 8x - 2
bl, bx, ebx	= 1E 4 = 30 8x - 2

sp, esp		= 26
bp, ebp		= 2E  # only 32 bit
si, esi		= 36
di, edi		= 3E

'mov reg8, 	[m16]'				: 			8A <reg_code> <m16l> <m16h>
'mov reg16, [m16]'				: 			8B <reg_code> <m16l> <m16h>
'mov reg32, [m16]'				: 	<32bc>	8B <reg_code> <m16l> <m16h>

'mov [m16],   <reg8>'			: 			88 <reg_code> <m16l> <m16h>
'mov [m16],   <reg16>'			: 			89 <reg_code> <m16l> <m16h>
'mov [m16],   <reg32>'			:  <32bc>	89 <reg_code> <m16l> <m16h>

reg_combination_codes:
<reg_combination_code>: byte, regX -> regX combination -> xy code

low_X_combinations: (C0 + <Y>(index) + <X> * 8) <X>(register) [ax, cx, dx, bx, sp, bp, si, di]
al, ax, eax -> <X>l, a<X>, e<X>x	: C0 + <X> * 8
cl, cx, ecx -> <X>l, a<X>, e<X>x	: C1 . . .
dl, dx, edx -> <X>l, a<X>, e<X>x	: C2 
bl, bx, ebx -> <X>l, a<X>, e<X>x	: C3
sp, esp 	-> <X>x, e<X>x			: C4
bp, ebp 	-> <X>x, e<X>x			: C5
si, esi 	-> <X>x, e<X>x			: C6
di, edi 	-> <X>x, e<X>x			: C7

high_byte_combinations: (E4 + <Y>(index) + <X> * 8)
E0, E1, E2, E3	: (low_X_combinations)
ah -> ah	: Meanless (E4)
ch -> ah	: E5
dh -> ah	: E6
bh -> ah	: E7
E8, E9, EA, EB	: (low_X_combinations)
ah -> ch	: EC
ch -> ch	: Meanless (ED)
dh -> ch	: EE
bh -> ch	: EF
F0, F1, F2, F3	: (low_X_combinations)
ah -> dh	: F4
ch -> dh	: F5
dh -> dh	: Meanless (F6)
bh -> dh	: F7
F8, F9, FA, FB	: (low_X_combinations)
ah -> bh	: FC
ch -> bh	: FD
dh -> bh	: FE
bh -> bh	: Meanless (FF)


#if high
	#then <reg_combination_code> = F(Y, X) = E4 + Y + X * 8
#else
	#then <reg_combination_code> = F(Y, X) = C0 + Y + X * 8
'mov reg8,  reg8'				:			88 <reg_combination_code>(high_byte_combinations,	
																	  low_X_combinations(without pointers))
'mov reg16, reg16'				:			89 <reg_combination_code>(low_X_combinations)
'mov reg32, reg32'				:	<32bc>	89 <reg_combination_code>(low_X_combinations)


'mov <ptr16>, <cons8>'			:			C6 06 <p16l> <p16h> <cons8>
'mov <ptr16>, <cons16>'			:			C7 06 <p16l> <p16h> <cons16>
'mov <ptr16>, <cons32>'			:	<32bc>	C7 06 <p16l> <p16h> <cons32>
# # # # - - - - - - - - - - - - # # # #```