-
Notifications
You must be signed in to change notification settings - Fork 81
/
gd32f1x0_it.c
244 lines (206 loc) · 7.89 KB
/
gd32f1x0_it.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
/*!
\file gd32f1x0_it.c
\brief interrupt service routines
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#include "gd32f1x0_it.h"
#include "systick.h"
__IO uint32_t step = 1;
/*!
\brief this function handles NMI exception
\param[in] none
\param[out] none
\retval none
*/
void NMI_Handler(void)
{
}
/*!
\brief this function handles HardFault exception
\param[in] none
\param[out] none
\retval none
*/
void HardFault_Handler(void)
{
/* if Hard Fault exception occurs, go to infinite loop */
while (1);
}
/*!
\brief this function handles MemManage exception
\param[in] none
\param[out] none
\retval none
*/
void MemManage_Handler(void)
{
/* if Memory Manage exception occurs, go to infinite loop */
while (1);
}
/*!
\brief this function handles BusFault exception
\param[in] none
\param[out] none
\retval none
*/
void BusFault_Handler(void)
{
/* if Bus Fault exception occurs, go to infinite loop */
while (1);
}
/*!
\brief this function handles UsageFault exception
\param[in] none
\param[out] none
\retval none
*/
void UsageFault_Handler(void)
{
/* if Usage Fault exception occurs, go to infinite loop */
while (1);
}
/*!
\brief this function handles SVC exception
\param[in] none
\param[out] none
\retval none
*/
void SVC_Handler(void)
{
}
/*!
\brief this function handles DebugMon exception
\param[in] none
\param[out] none
\retval none
*/
void DebugMon_Handler(void)
{
}
/*!
\brief this function handles PendSV exception
\param[in] none
\param[out] none
\retval none
*/
void PendSV_Handler(void)
{
}
/*!
\brief this function handles SysTick exception
\param[in] none
\param[out] none
\retval none
*/
void SysTick_Handler(void)
{
timer_event_software_generate(TIMER0,TIMER_EVENT_SRC_CMTG);
}
/*!
\brief this function handles TIMER0 interrupt request
\param[in] none
\param[out] none
\retval none
*/
void TIMER0_BRK_UP_TRG_COM_IRQHandler(void)
{
timer_interrupt_flag_clear(TIMER0, TIMER_INT_FLAG_CMT);
switch(step){
/* next step: step 2 configuration .A-C` breakover---------------------------- */
case 1:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_ENABLE);
step++;
break;
/* next step: step 3 configuration .B-C` breakover---------------------------- */
case 2:
/* channel0 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_ENABLE);
step++;
break;
/* next step: step 4 configuration .B-A` breakover---------------------------- */
case 3:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_ENABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
step++;
break;
/* next step: step 5 configuration .C-A` breakover---------------------------- */
case 4:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_ENABLE);
/* channel1 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
step++;
break;
/* next step: step 6 configuration .C-B` breakover---------------------------- */
case 5:
/* channel0 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_ENABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
step++;
break;
/* next step: step 1 configuration .A-B` breakover---------------------------- */
case 6:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_ENABLE);
/* channel2 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
step = 1;
break;
}
}