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fuse.log
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fuse.log
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Running: C:\Xilinx\14.1\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o C:/Users/eduar/OneDrive/Documents/Tutoriais_Blog/FPGA/Leitura_Encoder_e_Display_7_Segmentos/TestbenchEncoderValue_isim_beh.exe -prj C:/Users/eduar/OneDrive/Documents/Tutoriais_Blog/FPGA/Leitura_Encoder_e_Display_7_Segmentos/TestbenchEncoderValue_beh.prj work.TestbenchEncoderValue
ISim P.15xf (signature 0xc3576ebc)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "C:/Users/eduar/OneDrive/Documents/Tutoriais_Blog/FPGA/Leitura_Encoder_e_Display_7_Segmentos/Encoder_Rotativo_Teste.vhd" into library work
Parsing VHDL file "C:/Users/eduar/OneDrive/Documents/Tutoriais_Blog/FPGA/Leitura_Encoder_e_Display_7_Segmentos/TestbenchEncoderValue.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling architecture behavioral of entity Encoder_Rotativo_Teste [encoder_rotativo_teste_default]
Compiling architecture behavior of entity testbenchencodervalue
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 8 VHDL Units
Built simulation executable C:/Users/eduar/OneDrive/Documents/Tutoriais_Blog/FPGA/Leitura_Encoder_e_Display_7_Segmentos/TestbenchEncoderValue_isim_beh.exe
Fuse Memory Usage: 36324 KB
Fuse CPU Usage: 890 ms