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dds_1.xpr
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dds_1.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2015.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="10" Path="F:/hard_projects/wave_producer/dds_1/dds_1.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="899197c7e3504f40b813b8725fd38241"/>
<Option Name="Part" Val="xc7z020clg400-2"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="e:/soft_projects/fpga_minist/code/mnist_fpga-master/mnist_fpga-master/ipcore_dir"/>
<Option Name="IPRepoPath" Val="$PSRCDIR/sources_1/ip"/>
<Option Name="IPRepoPath" Val="$PSRCDIR/sources_1/ip/dds_addr"/>
<Option Name="IPRepoPath" Val="$PSRCDIR/sources_1"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PPRDIR/dds_1.ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PPRDIR/dds_1.ip_user_files/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/dds_main.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/matlab/rom.coe">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="dds_main"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/dds_testbench.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="dds_testbench"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="dds_addr_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_addr_0">
<File Path="$PSRCDIR/sources_1/ip/dds_addr_0/dds_addr_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="dds_addr_0_sim_netlist.v"/>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="dds_addr_0_stub.vhdl"/>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="sim/dds_addr_0.v"/>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="dds_addr.v"/>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="dds_addr_0.veo"/>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="dds_addr_0_stub.v"/>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="dds_addr_0.vho"/>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="dds_addr_0.xml"/>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="dds_addr_0_sim_netlist.vhdl"/>
<CompFileExtendedInfo CompFileName="dds_addr_0.xci" FileRelPathName="synth/dds_addr_0.v"/>
</File>
<Config>
<Option Name="TopModule" Val="dds_addr_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="rom" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rom">
<File Path="$PSRCDIR/sources_1/ip/rom/rom.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="f:/hard_projects/wave_producer/dds_1/matlab/rom.coe"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="rom.xml"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="synth/rom.vhd"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="sim/rom.vhd"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="rom.mif"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="summary.log"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="rom_ooc.xdc"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="rom_sim_netlist.vhdl"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="rom_sim_netlist.v"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="rom_stub.vhdl"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="rom_stub.v"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="rom.vho"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="doc/blk_mem_gen_v8_3_changelog.txt"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="blk_mem_gen_v8_3_1/simulation/blk_mem_gen_v8_3.vhd"/>
<CompFileExtendedInfo CompFileName="rom.xci" FileRelPathName="rom.veo"/>
</File>
<Config>
<Option Name="TopModule" Val="rom"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="dds_addr_0_synth_1" Type="Ft3:Synth" SrcSet="dds_addr_0" Part="xc7z020clg400-2" ConstrsSet="dds_addr_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/dds_addr_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="rom_synth_1" Type="Ft3:Synth" SrcSet="rom" Part="xc7z020clg400-2" ConstrsSet="rom" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/rom_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="dds_addr_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="dds_addr_0" Description="Vivado Implementation Defaults" SynthRun="dds_addr_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
<Run Id="rom_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="rom" Description="Vivado Implementation Defaults" SynthRun="rom_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>