The code presented in this repository was part of a paper written for the course "Metastability-Containing Hardware" which is taught by Dr. Moti Medina within the Faculty of Engineering at Bar Ilan University
This repository contains source files in VHDL language for the following systems:
- Sequence generator (8 bit) + TB
- Batcher's Odd-Even Sort Network + TB
- Asynchronous FIFO Queues + TB
- Full system integration + TB
To run the TB of the full system, please use EDA Playground.
Lenguage - VHDL
Libraries - none
Top Entity - System_interconnect_TB
Simulator - Aldec Riviera Pro 2022
Compile Options - -2019 -o
USING EPWave