/
ddrtests.py
executable file
·2529 lines (2365 loc) · 133 KB
/
ddrtests.py
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#!/usr/bin/env python
# -*- coding: utf-8 -*-
from __future__ import print_function
# Copyright (C) 2013, Elphel.inc.
# Tests for ddrc_test01.v, loosely following ddrc_test01_testbench.tf
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http:#www.gnu.org/licenses/>.
#
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2014, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
import mmap
import sys
import struct
import random
DRY_MODE= False # True
MONITOR_EMIO=False #True
def write_mem (addr, data):
global DEBUG_MODE;
if DRY_MODE:
print ("write_mem(0x%x,0x%x)"%(addr,data))
return
PAGE_SIZE=4096
endian="<" # little, ">" for big
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), PAGE_SIZE, offset=page_addr)
packedData=struct.pack(endian+"L",data)
d=struct.unpack(endian+"L",packedData)[0]
mm[page_offs:page_offs+4]=packedData
# print ("0x%08x <== 0x%08x (%d)"%(addr,d,d))
mm.close()
if MONITOR_EMIO and VEBOSE:
gpio0=read_mem (0xe000a068)
gpio1=read_mem (0xe000a06c)
print("GPIO: %04x %04x %04x %04x"%(gpio1>>16, gpio1 & 0xffff, gpio0>>16, gpio0 & 0xffff))
if ((gpio0 & 0xc) != 0xc) or ((gpio0 & 0xff00) != 0):
print("******** AXI STUCK ************")
exit (0)
def read_mem (addr):
if DRY_MODE:
print ("read_mem(0x%x)"%(addr))
return
PAGE_SIZE=4096
endian="<" # little, ">" for big
writeMode=len(sys.argv)>2
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), PAGE_SIZE, offset=page_addr)
data=struct.unpack(endian+"L",mm[page_offs:page_offs+4])
d=data[0]
# print ("0x%08x ==> 0x%08x (%d)"%(addr,d,d))
return d
mm.close()
# Define I/O addresses
use200Mhz=True;
PHASE_WIDTH = 8
CMD_PAUSE_BITS= 10
CMD_DONE_BIT= 10
CONTROL_ADDR = 0x1000 # AXI write address of control write registers
CONTROL_ADDR_MASK = 0x1400 # AXI write address of control registers
STATUS_ADDR = 0x1400 # AXI write address of status read registers
STATUS_ADDR_MASK = 0x1400 # AXI write address of status registers
BUSY_WR_ADDR = 0x1800 # AXI write address to generate busy
BUSY_WR_ADDR_MASK = 0x1c00 # AXI write address mask to generate busy
CMD0_ADDR = 0x0800 # AXI write to command sequence memory
CMD0_ADDR_MASK = 0x1800 # AXI read address mask for the command sequence memory
PORT0_RD_ADDR = 0x0000 # AXI read address to generate busy
PORT0_RD_ADDR_MASK = 0x1c00 # AXI read address mask to generate busy
PORT1_WR_ADDR = 0x0400 # AXI read address to generate busy
PORT1_WR_ADDR_MASK = 0x1c00 # AXI read address mask to generate busy
# #relative address parameters below to be ORed with CONTROL_ADDR and CONTROL_ADDR_MASK respectively
DLY_LD_REL = 0x080 # address to generate delay load
DLY_LD_REL_MASK = 0x380 # address mask to generate delay load
DLY_SET_REL = 0x070 # address to generate delay set
DLY_SET_REL_MASK = 0x3ff # address mask to generate delay set
RUN_CHN_REL = 0x000 # address to set sequnecer channel and run (4 LSB-s - channel)
RUN_CHN_REL_MASK = 0x3f0 # address mask to generate sequencer channel/run
PATTERNS_REL = 0x020 # address to set DQM and DQS patterns (160x0055)
PATTERNS_REL_MASK = 0x3ff # address mask to set DQM and DQS patterns
PATTERNS_TRI_REL = 0x021 # address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
PATTERNS_TRI_REL_MASK = 0x3ff # address mask to set DQM and DQS tristate patterns
WBUF_DELAY_REL = 0x022 # extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
WBUF_DELAY_REL_MASK = 0x3ff # address mask to set extra delay
PAGES_REL = 0x023 # address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
PAGES_REL_MASK = 0x3ff # address mask to set DQM and DQS patterns
CMDA_EN_REL = 0x024 # address to enable(0x825)/disable(0x824) command/address outputs
CMDA_EN_REL_MASK = 0x3fe # address mask for command/address outputs
SDRST_ACT_REL = 0x026 # address to activate(0x827)/deactivate(0x826) active-low reset signal to DDR3 memory
SDRST_ACT_REL_MASK = 0x3fe # address mask for reset DDR3
CKE_EN_REL = 0x028 # address to enable(0x829)/disable(0x828) CKE signal to memory
CKE_EN_REL_MASK = 0x3fe # address mask for command/address outputs
DCI_RST_REL = 0x02a # address to activate(0x82b)/deactivate(0x82a) Zynq DCI calibrate circuitry
DCI_RST_REL_MASK = 0x3fe # address mask for DCI calibrate circuitry
DLY_RST_REL = 0x02a # address to activate(0x82d)/deactivate(0x82c) delay calibration circuitry
DLY_RST_REL_MASK = 0x3fe # address mask for delay calibration circuitry
EXTRA_REL = 0x02e # address to set extra parameters (currently just inv_clk_div)
EXTRA_REL_MASK = 0x3ff # address mask for extra parameters
REFRESH_EN_REL = 0x030 # address to enable(0x31) and disable (0x30) DDR refresh
REFRESH_EN_REL_MASK = 0x3fe # address mask to enable/disable DDR refresh
REFRESH_PER_REL = 0x032 # address to set refresh period in 32 x tCK
REFRESH_PER_REL_MASK = 0x3ff # address mask set refresh period
REFRESH_ADDR_REL = 0x033 # address to set sequencer start address for DDR refresh
REFRESH_ADDR_REL_MASK = 0x3ff # address mask set refresh sequencer address
ADDRESS_NUMBER= 15
#BASEADDR = 0x40000000 # start of AXI GP0
BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2 # 0x0000 << 2
BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2 # 0x0000 << 2 = 0x000
BASEADDR_CMD0 = CMD0_ADDR << 2 # 0x0800 << 2 = 0x2000
BASEADDR_CTRL = (CONTROL_ADDR | BUSY_WR_ADDR) << 2 # with busy
BASEADDR_STATUS = STATUS_ADDR << 2 # 0x0800 << 2 = 0x2000
BASEADDR_DLY_LD = BASEADDR_CTRL | (DLY_LD_REL <<2) # 0x080, address to generate delay load
BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2) # 0x070, address to generate delay set
BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2) # 0x000, address to set sequnecer channel and run (4 LSB-s - channel)
BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2) # 0x020, address to set DQM and DQS patterns (160x0055)
BASEADDR_PATTERNS_TRI =BASEADDR_CTRL | (PATTERNS_TRI_REL<<2) # 0x021, address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
BASEADDR_WBUF_DELAY =BASEADDR_CTRL | (WBUF_DELAY_REL<<2) # 0x022, extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
BASEADDR_PAGES = BASEADDR_CTRL | (PAGES_REL<<2) # 0x023, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2) # 0x024, address to enable(0x825)/disable(0x824) command/address outputs
BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2) # 0x026 address to activate(0x827)/deactivate(0x826) active-low reset signal to DDR3 memory
BASEADDR_CKE_EN = BASEADDR_CTRL | (CKE_EN_REL<<2) # 0x028
BASEADDR_DCI_RST = BASEADDR_CTRL | (DCI_RST_REL<<2) # 0x02a (+1 - enable)
BASEADDR_DLY_RST = BASEADDR_CTRL | (DLY_RST_REL<<2) # 0x02c (+1 - enable)
BASEADDR_EXTRA = BASEADDR_CTRL | (EXTRA_REL<<2) # 0x02e, address to set extra parameters (currently just inv_clk_div)
BASEADDR_REFRESH_EN = BASEADDR_CTRL | (REFRESH_EN_REL<<2) # address to enable(0x31) and disable (0x30) DDR refresh
BASEADDR_REFRESH_PER = BASEADDR_CTRL | (REFRESH_PER_REL<<2) # address (0x32) to set refresh period in 32 x tCK
BASEADDR_REFRESH_ADDR = BASEADDR_CTRL | (REFRESH_ADDR_REL<<2) # address (0x33)to set sequencer start address for DDR refresh
BASEADDRESS_LANE0_ODELAY = BASEADDR_DLY_LD;
BASEADDRESS_LANE0_IDELAY = BASEADDR_DLY_LD+(0x10<<2)
BASEADDRESS_LANE1_ODELAY = BASEADDR_DLY_LD+(0x20<<2)
BASEADDRESS_LANE1_IDELAY = BASEADDR_DLY_LD+(0x30<<2)
BASEADDRESS_CMDA = BASEADDR_DLY_LD+(0x40<<2)
BASEADDRESS_PHASE = BASEADDR_DLY_LD+(0x60<<2)
STATUS_PSHIFTER_RDY_MASK = 0x100;
STATUS_LOCKED_MASK = 0x200;
STATUS_SEQ_BUSY_MASK = 0x400;
if use200Mhz:
DLY_LANE0_DQS_WLV_IDELAY = 0xb0 # idelay dqs
DLY_LANE1_DQS_WLV_IDELAY = 0xb0 # idelay dqs
DLY_LANE0_ODELAY= [0x98,0x4c,0x94,0x94,0x98,0x9c,0x92,0x99,0x98,0x94] # odelay dqm, odelay ddqs, odelay dq[7:0]
DLY_LANE0_IDELAY= [0x40,0x13,0x14,0x14,0x1c,0x13,0x14,0x13,0x1a] # idelay dqs, idelay dq[7:0
DLY_LANE1_ODELAY= [0x98,0x4c,0x98,0x98,0x98,0x9b,0x99,0xa8,0x9c,0x98] # odelay dqm, odelay ddqs, odelay dq[7:0]
DLY_LANE1_IDELAY= [0x40,0x2c,0x2b,0x2c,0x2c,0x34,0x30,0x33,0x30] # idelay dqs, idelay dq[7:0
DLY_CMDA= [0x3c,0x3c,0x3c,0x3c,0x3b,0x3a,0x39,0x38,0x34,0x34,0x34,0x34,0x33,0x32,0x31,0x30,
0x00,0x2c,0x2c,0x2c,0x2b,0x2a,0x29,0x28,0x24,0x24,0x24,0x24,0x23,0x22,0x21,0x20] # odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
# alternative to set same type delays to the same value
DLY_DQ_IDELAY = 0x20
DLY_DQ_ODELAY = 0xa0
DLY_DQS_IDELAY = 0x40
DLY_DQS_ODELAY = 0x4c #should match with phase write leveling
DLY_DM_ODELAY = 0xa0
DLY_CMDA_ODELAY =0x50
else:
DLY_LANE0_DQS_WLV_IDELAY = 0xe8 # idelay dqs
DLY_LANE1_DQS_WLV_IDELAY = 0xe8 # idelay dqs
DLY_LANE0_ODELAY= [0x74,0x74,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # odelay dqm, odelay ddqs, odelay dq[7:0]
DLY_LANE0_IDELAY= [0xd8,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # idelay dqs, idelay dq[7:0
DLY_LANE1_ODELAY= [0x74,0x74,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # odelay dqm, odelay ddqs, odelay dq[7:0]
DLY_LANE1_IDELAY= [0xd8,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # idelay dqs, idelay dq[7:0
DLY_CMDA= [0x5c,0x5c,0x5c,0x5c,0x5b,0x5a,0x59,0x58,0x54,0x54,0x54,0x54,0x53,0x52,0x51,0x50,
0x00,0x4c,0x4c,0x4c,0x4b,0x4a,0x49,0x48,0x44,0x44,0x44,0x44,0x43,0x42,0x41,0x40] # odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
# alternative to set same type delays to the same value
DLY_DQ_IDELAY = 0x20
DLY_DQ_ODELAY = 0xa0
DLY_DQS_IDELAY = 0x40
DLY_DQS_ODELAY = 0x4c #should match with phase write leveling
DLY_DM_ODELAY = 0xa0
DLY_CMDA_ODELAY =0x50
NUM_FINE_STEPS= 5
#`endif
DLY_PHASE= 0x2c # 0x1c # mmcm fine phase shift, 1/4 tCK
DQSTRI_FIRST= 0x3 # DQS tri-state control word, first when enabling output
DQSTRI_LAST= 0xc # DQS tri-state control word, first after disabling output
DQTRI_FIRST= 0x7 # DQ tri-state control word, first when enabling output
DQTRI_LAST= 0xe # DQ tri-state control word, first after disabling output
WBUF_DLY_DFLT= 0x6 # extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
WBUF_DLY_WLV= 0x7 # write leveling mode: extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
#DLY_PHASE= 80xdb # mmcm fine phase shift
INITIALIZE_OFFSET= 0x00 # moemory initialization start address (in words) ..`h0c
REFRESH_OFFSET= 0x10 # refresh start address (in words) ..`h13
WRITELEV_OFFSET= 0x20 # write leveling start address (in words) ..`h2a
READ_PATTERN_OFFSET=0x40 # read pattern to memory block sequence start address (in words) ..0x053 with 8x2*64 bits (variable)
WRITE_BLOCK_OFFSET= 0x100 # write block sequence start address (in words) ..0x14c
READ_BLOCK_OFFSET= 0x180 # read block sequence start address (in words)
VERBOSE=True
def check_args(n,command,args):
if len(args) != n:
if n==0:
print ("Error: command \"%s\" does not accept any arguments"%(command))
elif n==1:
print ("Error: command \"%s\" requires one argument"%(command))
else:
print ("Error: command \"%s\" requires %d arguments"%(command,n))
exit(1)
return
def axi_write_single(addr,data):
write_mem(0x40000000+addr,data)
def axi_read_addr(addr):
d= read_mem(0x40000000+addr)
return d
def read_status(): # task read_status;
global BASEADDR_STATUS
return axi_read_addr(BASEADDR_STATUS)
def wait_phase_shifter_ready(target_phase): # task wait_phase_shifter_ready;
global STATUS_PSHIFTER_RDY_MASK, PHASE_WIDTH,VERBOSE
if (VERBOSE): print("wait_phase_shifter_ready(0x%x)..."%target_phase,end="")
status = read_status()
while ((status & STATUS_PSHIFTER_RDY_MASK) == 0) or ((status ^ target_phase) & ((1<<PHASE_WIDTH)-1) != 0):
status=read_status()
if (VERBOSE): print("DONE")
def wait_sequencer_ready(): # task wait_sequencer_ready;
global STATUS_SEQ_BUSY_MASK,VERBOSE
if (VERBOSE): print("wait_sequencer_ready()...",end="")
# input integer num_skip; #skip this cycles before testing ready (latency from write to busy)
# repeat (num_skip) @(posedge CLK);
status=read_status()
# repeat (8) @(posedge CLK); # latency from read command to registered_rdata. TODO: make it certain (read with the same ID)
while (status & STATUS_SEQ_BUSY_MASK) != 0:
status= read_status()
if (VERBOSE): print("DONE")
def run_sequence (channel,start_addr):
global BASEADDR_RUN_CHN,VERBOSE
if (VERBOSE): print("run_sequence(0x%x,0x%x)"%(channel,start_addr))
axi_write_single(BASEADDR_RUN_CHN+(channel<<2), start_addr)
def run_mrs(): # task run_mrs;
global INITIALIZE_OFFSET, VERBOSE
if (VERBOSE): print("RUN MRS")
run_sequence(0,INITIALIZE_OFFSET)
def run_write_lev(): # task run_write_lev;
global WRITELEV_OFFSET, VERBOSE
if (VERBOSE): print("RUN WRITE LEVELING")
run_sequence(0,WRITELEV_OFFSET)
def run_read_pattern(): # task run_read_pattern;
global READ_PATTERN_OFFSET, VERBOSE
if (VERBOSE): print("RUN READ PATTERN")
run_sequence(0,READ_PATTERN_OFFSET)
def run_write_block(): # task run_write_block;
global WRITE_BLOCK_OFFSET, VERBOSE
if (VERBOSE): print("RUN WRITE BLOCK")
run_sequence(1,WRITE_BLOCK_OFFSET)
def run_read_block(): # task run_read_block;
global READ_BLOCK_OFFSET, VERBOSE
if (VERBOSE): print("RUN READ BLOCK")
run_sequence(0,READ_BLOCK_OFFSET)
def enable_cmda(en):
global BASEADDR_CMDA_EN
if en:
axi_write_single(BASEADDR_CMDA_EN+4, 0)
else:
axi_write_single(BASEADDR_CMDA_EN, 0)
def enable_cke(en):
global BASEADDR_CKE_EN
if en:
axi_write_single(BASEADDR_CKE_EN+4, 0)
else:
axi_write_single(BASEADDR_CKE_EN, 0)
def activate_sdrst(en):
global BASEADDR_SDRST_ACT
if en:
axi_write_single(BASEADDR_SDRST_ACT+4, 0)
else:
axi_write_single(BASEADDR_SDRST_ACT, 0)
def enable_refresh(en):
global BASEADDR_REFRESH_EN
if en:
axi_write_single(BASEADDR_REFRESH_EN+4, 0)
else:
axi_write_single(BASEADDR_REFRESH_EN, 0)
def write_block_buf():
global BASEADDR_PORT1_WR, VERBOSE
if (VERBOSE): print("WRITE BLOCK DATA")
for i in range(256):
d=i | (((i + 7) & 0xff) << 8) | (((i + 23) & 0xff) << 16) | (((i + 31) & 0xff) << 24)
axi_write_single(BASEADDR_PORT1_WR+(i<<2), d)
# if (VERBOSE): print("Write block data (addr:data): 0x%x:0x%x "%(BASEADDR_PORT1_WR+(i<<2),d))
def read_block_buf(
num_read ): #input integer num_read; // number of words to read (will be rounded up to multiple of 16)
global BASEADDR_PORT0_RD, VERBOSE
buf=[]
for i in range(num_read):
d=axi_read_addr(BASEADDR_PORT0_RD+(i<<2))
buf.append(d)
if (VERBOSE): print("Read block data (addr:data): 0x%x:0x%x "%(BASEADDR_PORT0_RD+(i<<2),d))
return buf
def read_buf(
num_read ): #input integer num_read; // number of words to read (will be rounded up to multiple of 16)
global BASEADDR_PORT0_RD, VERBOSE;
buf=[]
for i in range(num_read):
d=axi_read_addr(BASEADDR_PORT0_RD+(i<<2))
buf.append(d)
if (VERBOSE):
for i in range(num_read):
addr= i<<2;
if (i%8) == 0:
print ("\n%08x: "%addr,end="")
print ("%08x "%buf[i],end="")
print ()
return buf
def encode_seq_word(
phy_addr_in, # [14:0] also provides pause length when the command is NOP
phy_bank_in, # [ 2:0] bank address
phy_rcw_in, # [ 2:0] {ras,cas,we}
phy_odt_in, # may be optimized?
phy_cke_inv, # invert CKE
phy_sel_in, # first/second half-cycle, other will be nop (cke+odt applicable to both)
phy_dq_en_in,
phy_dqs_en_in,
phy_dqs_toggle_en, # enable toggle DQS according to the pattern
phy_dci_en_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
phy_buf_wr, # connect to external buffer
phy_buf_rd, # connect to external buffer
add_nop): # add NOP after the current command, keep other data
return (
((phy_addr_in & 0x7ffff) << 17) | # phy_addr_in[14:0]
((phy_bank_in & 0x7) << 14) | # phy_bank_in[2:0],
((phy_rcw_in & 0x7) << 11) | # phy_rcw_in[2:0], # {ras,cas,we}, positive logic (3'b0 - NOP)
((phy_odt_in & 0x1) << 10) | # phy_odt_in
((phy_cke_inv & 0x1) << 9) | # phy_cke_inv # invert CKE
((phy_sel_in & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((phy_dq_en_in & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((phy_dqs_en_in & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((phy_dqs_toggle_en&0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((phy_dci_en_in & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((phy_buf_wr & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((phy_buf_rd & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((add_nop & 0x1) << 1) | # add_nop # add NOP after the current command, keep other data
0) # Reserved for future use
def encode_seq_skip(
skip, # [CMD_PAUSE_BITS-1:0] - number of skip cycles in additiona to 1 (0 - 1 cycle, 1 - 2, ...)
done, # 1 - end of sequence
dci_en, # enable DCI
odt_en): # enavble ODT
global CMD_DONE_BIT,CMD_PAUSE_BITS
return (
((done & 1) << (CMD_DONE_BIT+17)) | # 14-CMD_DONE_BIT{1'b0}},
((skip & ((1<< CMD_PAUSE_BITS)-1)) << 17) | # skip[CMD_PAUSE_BITS-1:0]
# 3'b0, #phy_bank_in[2:0],
# 3'b0, # phy_rcw_in[2:0], # {ras,cas,we}
((odt_en & 0x1) << 10) | # odt_en, # phy_odt_in,
# 1'b0, # phy_cke_in, # may be optimized?
# 1'b0, # phy_sel_in, # first/second half-cycle, other will be nop (cke+odt applicable to both)
# 1'b0, # phy_dq_en_in, #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
# 1'b0, # phy_dqs_en_in, #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
# 1'b0, #enable toggle DQS according to the pattern
((dci_en & 0x1) << 4) # dci_en, # phy_dci_en_in, #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
# 1'b0, # phy_buf_wr, # connect to external buffer (but only if not paused)
# 1'b0, # phy_buf_rd, # connect to external buffer (but only if not paused)
# 1'b0, # add NOP after the current command, keep other data
# 1'b0 # Reserved for future use
)
# Set MR3, read nrep*8 words, save to buffer (port0). No ACTIVATE/PRECHARGE are needed/allowed
def set_read_pattern( # task set_read_pattern;
nrep, # input integer nrep;
npat, #trying pattern type (only 0 defined)
scnd):#adjusting first/seccond
# reg [31:0] cmd_addr;
# reg [31:0] data;
# reg [17:0] mr3_norm;
# reg [17:0] mr3_pattern;
# integer i;
global BASEADDR_CMD0, READ_PATTERN_OFFSET
cmd_addr = BASEADDR_CMD0 + (READ_PATTERN_OFFSET << 2)
mr3_norm = ddr3_mr3 (
0, #1'h0, # mpr; # MPR mode: 0 - normal, 1 - dataflow from MPR
0) # 2'h0) # [1:0] mpr_rf; # MPR read function: 2'b00: predefined pattern 0101...
mr3_pattern = ddr3_mr3 (
1, # 1'h1, # mpr; # MPR mode: 0 - normal, 1 - dataflow from MPR
npat & 3) # 2'h0) # [1:0] mpr_rf; # MPR read function: 2'b00: predefined pattern 0101...
# Set pattern mode
data = encode_seq_word(
mr3_pattern & 0x7fff, # mr3[14:0], # [14:0] phy_addr_in;
(mr3_pattern >> 15) & 0x7, # mr3[17:15], # [ 2:0] phy_bank_in; #TODO: debug!
7, # 3'b111, # [ 2:0] phy_rcw_in; # {ras,cas,we}, positive
0, # 1'b0, # phy_odt_in; # may be optimized?
0, # 1'b0, # phy_cke_inv; # may be optimized?
0, # 1'b0, # phy_sel_in; # first/second half-cycle, other will be nop (cke+odt applicable to both)
0, # 1'b0, # phy_dq_en_in;
0, # 1'b0, # phy_dqs_en_in;
0, # 1'b0, # phy_dqs_toggle_en;
0, # 1'b0, # phy_dci_en_in; # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
0, # 1'b0, # phy_buf_wr; # connect to external buffer
0, # 1'b0, # phy_buf_rd; # connect to external buffer
0) # 1'b0) # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# data = encode_seq_skip(5,0,0,0) # tMOD
data = encode_seq_skip(5,0,1,0) # tMOD Early DCI
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# first read
# read
data = (
((0 & 0x3ff) << 17) | # ra[14:0]
((0 & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x2 & 0x7) << 11) | # 3'b010, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((0 & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
#repeat remaining reads
for i in range (1,nrep): # for (i=1;i<nrep;i=i+1) begin
# read
data = (
((0 & 0x3ff) << 17) | # cra[9:0]
((0 & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x2 & 0x7) << 11) | # 3'b010, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
(( 1 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((0 & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((0 & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((0 & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
# (( 1 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
data = encode_seq_skip(2,0,1,0) # keep dci enabled
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# Turn off read pattern mode
data = encode_seq_word(
mr3_norm & 0x7fff, # mr3[14:0], # [14:0] phy_addr_in;
(mr3_norm >> 15) & 0x7, # mr3[17:15], # [ 2:0] phy_bank_in; #TODO: debug!
7, # 3'b111, # [ 2:0] phy_rcw_in; # {ras,cas,we}, positive
0, # 1'b0, # phy_odt_in; # may be optimized?
0, # 1'b0, # phy_cke_inv; # may be optimized?
0, # 1'b0, # phy_sel_in; # first/second half-cycle, other will be nop (cke+odt applicable to both)
0, # 1'b0, # phy_dq_en_in;
0, # 1'b0, # phy_dqs_en_in;
0, # 1'b0, # phy_dqs_toggle_en;
1, # 1'b1, # phy_dci_en_in;
0, # 1'b0, # phy_buf_wr; # connect to external buffer
0, # 1'b0, # phy_buf_rd; # connect to external buffer
0) # 1'b0) # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
data = encode_seq_skip(5,0,1,0 ) # tMOD (keep DCI enabled)
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# Turn off DCI
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((0 & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
data = encode_seq_skip(0,1,0,0) # end of sequence (no dci, no odt)
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
def set_read_block(
ba, # [ 2:0] bank address
ra, # [14:0] row address
ca, # [ 9:0] column address
scnd): # use second (delayed) clock for read command
# cmd_addr, # command address (bit 10 - auto/manual banks)
# data): # [31:0] - command data
global BASEADDR_CMD0, READ_BLOCK_OFFSET
# integer i;
cmd_addr = BASEADDR_CMD0 + (READ_BLOCK_OFFSET << 2)
# activate
data = (
((ra & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x4 & 0x7) << 11) | # 3'b100, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# see if pause is needed . See when buffer read should be started - maybe before WR command
# data = encode_seq_skip(1,0,0,0)
data = encode_seq_skip(1,0,1,0) #early DCI enable
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# first read
# read
data = (
((ca & 0x3ff) << 17) | # ca[9:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x2 & 0x7) << 11) | # 3'b010, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
#repeat remaining reads
for i in range (1,64):
# read
data = (
(((ca + (i<<3)) & 0x3ff) << 17) | # {5'b0,ca[9:0]} + (i<<3),
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x2 & 0x7) << 11) | # 3'b010, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
(( 1 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# tRTP = 4*tCK is already satisfied, no skip here
# precharge
data = (
((ra & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x5 & 0x7) << 11) | # 3'b101, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
(( 1 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
data = encode_seq_skip(2,0,1,0) # keep DCI
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
data = encode_seq_skip(0,1,0,0) # end of sequence . TODO: verify DCI is disabled here - yes, OK
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
def set_write_block(
ba, # input [ 2:0] ba;
ra, # input [14:0] ra;
ca): # input [ 9:0] ca;
# reg [31:0] cmd_addr;
# reg [31:0] data;
# integer i;
global BASEADDR_CMD0, WRITE_BLOCK_OFFSET,VERBOSE
if (VERBOSE): print("set_write_block(0x%x,0x%x,0x%x"%(ba,ra,ca))
cmd_addr = BASEADDR_CMD0 + (WRITE_BLOCK_OFFSET << 2)
# activate
data = (
((ra & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x4 & 0x7) << 11) | # 3'b100, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# see if pause is needed . See when buffer read should be started - maybe before WR command
# data = encode_seq_skip(1,0,0,0) # tRCD
data = encode_seq_skip(2,0,0,0) # tRCD
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# first write
# write
data = (
((ca & 0x3ff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x3 & 0x7) << 11) | # 3'b011, # phy_rcw_in[2:0], # {ras,cas,we}
(( 1 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
# (( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
# ((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
# ((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
# (( 1 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
(( 1 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
(( 1 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
(( 1 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
#repeat remaining writes
for i in range (1,64):
# write
data = (
(((ca + (i<<3)) & 0x3ff) << 17) | # {5'b0,ca[9:0]} + (i<<3),
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x3 & 0x7) << 11) | # 3'b011, # phy_rcw_in[2:0], # {ras,cas,we}
(( 1 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
# (( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
# (( 0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
(( 1 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
(( 1 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
(( 1 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
(( 1 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
(( 1 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
(( 1 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
(( 1 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
(( 1 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
# (( 1 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
# (( 0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
#this is one extra read, needed because of BRAM latency
(( 1 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# nop
data = (
((0 & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
(( 1 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
(( 1 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
(( 1 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# ODT off, it has latency
data = encode_seq_skip(2,0,0,0) # tWR = 15ns (6 cycles for 2.5ns) from end of write (not write command)
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
# precharge, ODT off
data = (
((ra & 0x7fff) << 17) | # ra[14:0]
((ba & 0x7) << 14) | # ba[2:0], #phy_bank_in[2:0],
((0x5 & 0x7) << 11) | # 3'b101, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
((0 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
((0 & 0x1) << 4) | # phy_dci_en_in #phy_dci_in, # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 3) | # phy_buf_wr # connect to external buffer (but only if not paused)
((0 & 0x1) << 2) | # phy_buf_rd # connect to external buffer (but only if not paused)
((0 & 0x1) << 1)) # add_nop # add NOP after the current command, keep other data
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
data = encode_seq_skip(2,0,0,0) #
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
data = encode_seq_skip(0,1,0,0) # end of sequence
axi_write_single(cmd_addr, data)
cmd_addr = cmd_addr + 4
def ddr3_mr0( # function [ADDRESS_NUMBER+2:0] ddr3_mr0;
pd, # input pd; # precharge power down 0 - dll off (slow exit), 1 - dll on (fast exit)
wr, # input [2:0] wr; # write recovery:
# 3'b000: 16
# 3'b001: 5
# 3'b010: 6
# 3'b011: 7
# 3'b100: 8
# 3'b101: 10
# 3'b110: 12
# 3'b111: 14
dll_rst, # input dll_rst; # 1 - dll reset (self clearing bit)
cl, # input [3:0] cl; # CAS latency (>=15ns):
# 0000: reserved
# 0010: 5
# 0100: 6
# 0110: 7
# 1000: 8
# 1010: 9
# 1100: 10
# 1110: 11
# 0001: 12
# 0011: 13
# 0101: 14
bt, # input bt; # read burst type: 0 sequential (nibble), 1 - interleaved
bl): #input [1:0] bl; # burst length:
# 2'b00 - fixed BL8
# 2'b01 - 4 or 8 on-the-fly by A12
# 2'b10 - fixed BL4 (chop)
# 2'b11 - reserved
global ADDRESS_NUMBER
return (
# 3'b0,
# {ADDRESS_NUMBER-13{1'b0}},
((pd & 1) << 12) | # pd, # MR0.12
((wr & 7) << 9) | # wr, # MR0.11_9
((dll_rst & 1) << 8) | # dll_rst, # MR0.8
(0 << 7) | # 1'b0, # MR0.7
(((cl >>1) & 7)<< 4) | # cl[3:1], # MR0.6_4
((bt & 1) << 3) | # bt, # MR0.3
((cl & 1) << 2) | # cl[0], # MR0.2
((bl & 3) << 0)) # bl[1:0]}; # MR0.1_0
def ddr3_mr1( # function [ADDRESS_NUMBER+2:0] ddr3_mr1;
qoff, # input qoff; # output enable: 0 - DQ, DQS operate in normal mode, 1 - DQ, DQS are disabled
tdqs, #input tdqs; # termination data strobe (for x8 devices) 0 - disabled, 1 - enabled
rtt, #input [2:0] rtt; # on-die termination resistance: