Update for Vivado 2017.4 & uhd-fpga master branch?

[ejk43]

Hi guys,

Looking to test out this channelizer...

Is there any plan to update IP to Vivado 2017.4 and target the uhd-fpga master branch? I think the only major difference ought to be the axi_wrapper, but I'm not 100% sure.

EJ

[mmehari]

What about multiple driver net problem? I found the error "DRC MDRV-1 multiple driver nets error" while compiling the channelizer block using Vivado 2017.4. The net having multiple drivers is "phase_d[0]" in pfb_2x.v file, which is driven by two sources (net rd_addr[8:0] in line 89 and net phase in line 203).

Do you also have the same issue?

Michael T