S5E7870-cmu.c

#include "../pwrcal.h"
#include "../pwrcal-clk.h"
#include "../pwrcal-env.h"
#include "../pwrcal-rae.h"
#include "../pwrcal-pmu.h"
#include "S5E7870-cmusfr.h"
#include "S5E7870-pmusfr.h"
#include "S5E7870-cmu.h"

#ifdef PWRCAL_TARGET_LINUX
#include <soc/samsung/ect_parser.h>
#else
#include <mach/ect_parser.h>
#endif

#define PLL_RATE_MPS(_rate, _m, _p, _s)	\
	{				\
		.rate	=	(_rate),	\
		.mdiv	=	(_m),	\
		.pdiv	=	(_p),	\
		.sdiv	=	(_s),	\
	}

#define PLL_RATE_MPSK(_rate, _m, _p, _s, _k)	\
	{				\
		.rate	=	(_rate),	\
		.mdiv	=	(_m),	\
		.pdiv	=	(_p),	\
		.sdiv	=	(_s),	\
		.kdiv	=	(_k),	\
	}

extern struct pwrcal_pll_ops pll141xx_ops;
extern struct pwrcal_pll_ops pll1431x_ops;

struct pwrcal_clk *fixed_rate_type_list[NUM_OF_FIXED_RATE_TYPE];
struct pwrcal_clk *fixed_factor_type_list[NUM_OF_FIXED_FACTOR_TYPE];
struct pwrcal_clk *pll_type_list[NUM_OF_PLL_TYPE];
struct pwrcal_clk *mux_type_list[NUM_OF_MUX_TYPE];
struct pwrcal_clk *div_type_list[NUM_OF_DIV_TYPE];
struct pwrcal_clk *gate_type_list[NUM_OF_GATE_TYPE];

#define ADD_CLK_TO_LIST(to, x)	to[clk_##x.clk.id & 0xFFF] = &(clk_##x.clk)

CLK_PLL(14170,	CPUCL0_PLL,	0,	CPUCL0_PLL_LOCK,	CPUCL0_PLL_CON0,	NULL,	CPUCL0_MUX_CPUCL0_PLL,	&pll141xx_ops);
CLK_PLL(14170,	CPUCL1_PLL,	0,	CPUCL1_PLL_LOCK,	CPUCL1_PLL_CON0,	NULL,	CPUCL1_MUX_CPUCL1_PLL,	&pll141xx_ops);
CLK_PLL(14170,	MEM_PLL,	0,	MEM_PLL_LOCK,	MEM_PLL_CON0,	NULL,	MIF_MUX_MEM_PLL,	&pll141xx_ops);
CLK_PLL(14170,	BUS_PLL,	0,	BUS_PLL_LOCK,	BUS_PLL_CON0,	NULL,	MIF_MUX_BUS_PLL,	&pll141xx_ops);
CLK_PLL(14170,	MEDIA_PLL,	0,	MEDIA_PLL_LOCK,	MEDIA_PLL_CON0,	NULL,	MIF_MUX_MEDIA_PLL,	&pll141xx_ops);
CLK_PLL(14180,	G3D_PLL,	0,	G3D_PLL_LOCK,	G3D_PLL_CON0,	NULL,	G3D_MUX_G3D_PLL,	&pll141xx_ops);
CLK_PLL(14180,	USB_PLL,	0,	USB_PLL_LOCK,	USB_PLL_CON0,	NULL,	FSYS_MUX_USB_PLL,	&pll141xx_ops);
CLK_PLL(14180,	ISP_PLL,	0,	ISP_PLL_LOCK,	ISP_PLL_CON0,	NULL,	ISP_MUX_ISP_PLL,	&pll141xx_ops);
CLK_PLL(14180,	DISP_PLL,	0,	DISP_PLL_LOCK,	DISP_PLL_CON0,	NULL,	DISPAUD_MUX_DISP_PLL,	&pll141xx_ops);
CLK_PLL(14310,	AUD_PLL,	0,	AUD_PLL_LOCK,	AUD_PLL_CON0,	NULL,	DISPAUD_MUX_AUD_PLL,	&pll1431x_ops);


FIXEDRATE(OSCCLK,	26 * MHZ,	0);
FIXEDRATE(OSCCLK_26M,	26 * MHZ,	0);
FIXEDRATE(CLKPHY_FSYS_USB20DRD_PHYCLOCK,	60 * MHZ,	0);
FIXEDRATE(CLKPHY_FSYS_UFS_TX0_SYMBOL,	300 * MHZ,	0);
FIXEDRATE(CLKPHY_FSYS_UFS_RX0_SYMBOL,	300 * MHZ,	0);
FIXEDRATE(CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS,	188 * MHZ,	0);
FIXEDRATE(CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0,	188 * MHZ,	0);
FIXEDRATE(CLKIO_DISPAUD_AUDIOCDCLK0,	100 * MHZ,	0);
FIXEDRATE(CLKIO_DISPAUD_MIXER_SCLK_AP,	12.5 * MHZ,	0);
FIXEDRATE(CLKIO_DISPAUD_MIXER_BCLK_BT,	12.5 * MHZ,	0);
FIXEDRATE(CLKIO_DISPAUD_MIXER_BCLK_CP,	12.5 * MHZ,	0);
FIXEDRATE(CLKIO_DISPAUD_MIXER_BCLK_FM,	12.5 * MHZ,	0);
FIXEDRATE(CLKPHY_ISP_S_RXBYTECLKHS0_S4,	188 * MHZ,	0);
FIXEDRATE(CLKPHY_ISP_S_RXBYTECLKHS0_S4S,	188 * MHZ,	0);
FIXEDRATE(FIN_TEMP,	24 * MHZ,	0);

FIXEDFACTOR(MIF_FF_MUX_MEM_PLL_DIV2,	MIF_MUX_MEM_PLL,	2,	0);
FIXEDFACTOR(MIF_FF_MUX_MEDIA_PLL_DIV2,	MIF_MUX_MEDIA_PLL,	2,	0);
FIXEDFACTOR(MIF_FF_MUX_BUS_PLL_DIV2,	MIF_MUX_BUS_PLL,	2,	0);

static struct pwrcal_clk *cpucl0_mux_cpucl0_pll_p[] = {CLK(OSCCLK), CLK(CPUCL0_PLL)};
static struct pwrcal_clk *cpucl0_mux_clkcmu_cpucl0_switch_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_CPUCL0_SWITCH)};
static struct pwrcal_clk *cpucl0_mux_clk_cpucl0_p[] = {CLK(CPUCL0_MUX_CPUCL0_PLL), CLK(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER)};
static struct pwrcal_clk *cpucl1_mux_cpucl1_pll_p[] = {CLK(OSCCLK), CLK(CPUCL1_PLL)};
static struct pwrcal_clk *cpucl1_mux_clkcmu_cpucl1_switch_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_CPUCL1_SWITCH)};
static struct pwrcal_clk *cpucl1_mux_clk_cpucl1_p[] = {CLK(CPUCL1_MUX_CPUCL1_PLL), CLK(CPUCL1_MUX_CLKCMU_CPUCL1_SWITCH_USER)};
static struct pwrcal_clk *dispaud_mux_disp_pll_p[] = {CLK(OSCCLK), CLK(DISP_PLL)};
static struct pwrcal_clk *dispaud_mux_aud_pll_p[] = {CLK(OSCCLK), CLK(AUD_PLL)};
static struct pwrcal_clk *dispaud_mux_clkcmu_dispaud_bus_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_DISPAUD_BUS)};
static struct pwrcal_clk *dispaud_mux_clkcmu_dispaud_decon_int_vclk_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK)};
static struct pwrcal_clk *dispaud_mux_clkcmu_dispaud_decon_int_eclk_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_ECLK)};
static struct pwrcal_clk *dispaud_mux_clk_dispaud_decon_int_vclk_p[] = {CLK(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER), CLK(DISPAUD_MUX_DISP_PLL)};
static struct pwrcal_clk *dispaud_mux_clk_dispaud_decon_int_eclk_p[] = {CLK(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER), CLK(DISPAUD_MUX_DISP_PLL)};
static struct pwrcal_clk *dispaud_mux_clkphy_dispaud_mipiphy_txbyteclkhs_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS)};
static struct pwrcal_clk *dispaud_mux_clkphy_dispaud_mipiphy_rxclkesc0_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0)};
static struct pwrcal_clk *dispaud_mux_clk_dispaud_mi2s_p[] = {CLK(DISPAUD_MUX_AUD_PLL), CLK(CLKIO_DISPAUD_AUDIOCDCLK0)};
static struct pwrcal_clk *fsys_mux_usb_pll_p[] = {CLK(OSCCLK), CLK(USB_PLL)};
static struct pwrcal_clk *fsys_mux_clkphy_fsys_usb20drd_phyclock_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_FSYS_USB20DRD_PHYCLOCK)};
static struct pwrcal_clk *fsys_mux_clkphy_fsys_ufs_tx0_symbol_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_FSYS_UFS_TX0_SYMBOL)};
static struct pwrcal_clk *fsys_mux_clkphy_fsys_ufs_rx0_symbol_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_FSYS_UFS_RX0_SYMBOL)};
static struct pwrcal_clk *g3d_mux_g3d_pll_p[] = {CLK(OSCCLK), CLK(G3D_PLL)};
static struct pwrcal_clk *g3d_mux_clkcmu_g3d_switch_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_G3D_SWITCH)};
static struct pwrcal_clk *g3d_mux_clk_g3d_p[] = {CLK(G3D_MUX_G3D_PLL), CLK(G3D_MUX_CLKCMU_G3D_SWITCH_USER)};
static struct pwrcal_clk *isp_mux_isp_pll_p[] = {CLK(OSCCLK), CLK(ISP_PLL)};
static struct pwrcal_clk *isp_mux_clkcmu_isp_vra_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_ISP_VRA)};
static struct pwrcal_clk *isp_mux_clkcmu_isp_cam_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_ISP_CAM)};
static struct pwrcal_clk *isp_mux_clkcmu_isp_isp_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_ISP_ISP)};
static struct pwrcal_clk *isp_mux_clk_isp_vra_p[] = {CLK(ISP_MUX_CLKCMU_ISP_VRA_USER), CLK(ISP_MUX_ISP_PLL)};
static struct pwrcal_clk *isp_mux_clk_isp_cam_p[] = {CLK(ISP_MUX_CLKCMU_ISP_CAM_USER), CLK(ISP_MUX_ISP_PLL)};
static struct pwrcal_clk *isp_mux_clk_isp_isp_p[] = {CLK(ISP_MUX_CLKCMU_ISP_ISP_USER), CLK(ISP_MUX_ISP_PLL)};
static struct pwrcal_clk *isp_mux_clk_isp_ispd_p[] = {CLK(ISP_MUX_CLK_ISP_VRA), CLK(ISP_MUX_CLK_ISP_CAM)};
static struct pwrcal_clk *isp_mux_clkphy_isp_s_rxbyteclkhs0_s4_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_ISP_S_RXBYTECLKHS0_S4)};
static struct pwrcal_clk *isp_mux_clkphy_isp_s_rxbyteclkhs0_s4s_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_ISP_S_RXBYTECLKHS0_S4S)};
static struct pwrcal_clk *mfcmscl_mux_clkcmu_mfcmscl_mscl_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_MFCMSCL_MSCL)};
static struct pwrcal_clk *mfcmscl_mux_clkcmu_mfcmscl_mfc_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_MFCMSCL_MFC)};
static struct pwrcal_clk *mif_mux_mem_pll_p[] = {CLK(OSCCLK), CLK(MEM_PLL)};
static struct pwrcal_clk *mif_mux_media_pll_p[] = {CLK(OSCCLK), CLK(MEDIA_PLL)};
static struct pwrcal_clk *mif_mux_bus_pll_p[] = {CLK(OSCCLK), CLK(BUS_PLL)};
static struct pwrcal_clk *mif_mux_clk_mif_phy_clk2x_p[] = {CLK(MIF_MUX_MEM_PLL), CLK(MIF_MUX_CLK_MIF_PHY_SWITCH)};
static struct pwrcal_clk *mif_mux_clk_mif_phy_switch_p[] = {CLK(MIF_MUX_MEDIA_PLL), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clk_mif_busd_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2), CLK(MIF_FF_MUX_MEM_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clk_mif_cci_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2), CLK(MIF_MUX_BUS_PLL)};
static struct pwrcal_clk *mif_mux_clkcmu_isp_vra_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2), CLK(MIF_MUX_BUS_PLL)};
static struct pwrcal_clk *mif_mux_clkcmu_isp_cam_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_isp_isp_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_dispaud_bus_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_dispaud_decon_int_vclk_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_dispaud_decon_int_eclk_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_mfcmscl_mscl_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2), CLK(MIF_MUX_BUS_PLL)};
static struct pwrcal_clk *mif_mux_clkcmu_mfcmscl_mfc_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2), CLK(MIF_MUX_BUS_PLL)};
static struct pwrcal_clk *mif_mux_clkcmu_fsys_bus_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_fsys_mmc0_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_fsys_mmc1_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_fsys_mmc2_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_fsys_ufsunipro_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_fsys_ufsunipro_cfg_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_fsys_usb20drd_refclk_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_peri_bus_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_peri_uart_btwififm_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_peri_uart_debug_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_peri_uart_sensor_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(MIF_FF_MUX_MEDIA_PLL_DIV2)};
static struct pwrcal_clk *mif_mux_clkcmu_peri_spi_frontfrom_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(OSCCLK)};
static struct pwrcal_clk *mif_mux_clkcmu_peri_spi_rearfrom_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(OSCCLK)};
static struct pwrcal_clk *mif_mux_clkcmu_peri_spi_ese_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(OSCCLK)};
static struct pwrcal_clk *mif_mux_clkcmu_peri_spi_voiceprocessor_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(OSCCLK)};
static struct pwrcal_clk *mif_mux_clkcmu_peri_spi_sensorhub_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(OSCCLK)};
static struct pwrcal_clk *mif_mux_clkcmu_isp_sensor0_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(OSCCLK)};
static struct pwrcal_clk *mif_mux_clkcmu_isp_sensor1_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(OSCCLK)};
static struct pwrcal_clk *mif_mux_clkcmu_isp_sensor2_p[] = {CLK(MIF_FF_MUX_BUS_PLL_DIV2), CLK(OSCCLK)};



CLK_MUX(CPUCL0_MUX_CPUCL0_PLL, cpucl0_mux_cpucl0_pll_p, CLK_CON_MUX_CPUCL0_PLL, 12, 1, CLK_STAT_MUX_CPUCL0_PLL, 12, 2, CLK_CON_MUX_CPUCL0_PLL, 21, 0);
CLK_MUX(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER, cpucl0_mux_clkcmu_cpucl0_switch_user_p, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_USER, 12, 1, CLK_STAT_MUX_CLKCMU_CPUCL0_SWITCH_USER, 12, 2, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_USER, 21, 0);
CLK_MUX(CPUCL0_MUX_CLK_CPUCL0, cpucl0_mux_clk_cpucl0_p, CLK_CON_MUX_CLK_CPUCL0, 12, 1, CLK_STAT_MUX_CLK_CPUCL0, 12, 2, CLK_CON_MUX_CLK_CPUCL0, 21, 0);
CLK_MUX(CPUCL1_MUX_CPUCL1_PLL, cpucl1_mux_cpucl1_pll_p, CLK_CON_MUX_CPUCL1_PLL, 12, 1, CLK_STAT_MUX_CPUCL1_PLL, 12, 2, CLK_CON_MUX_CPUCL1_PLL, 21, 0);
CLK_MUX(CPUCL1_MUX_CLKCMU_CPUCL1_SWITCH_USER, cpucl1_mux_clkcmu_cpucl1_switch_user_p, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_USER, 12, 1, CLK_STAT_MUX_CLKCMU_CPUCL1_SWITCH_USER, 12, 2, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_USER, 21, 0);
CLK_MUX(CPUCL1_MUX_CLK_CPUCL1, cpucl1_mux_clk_cpucl1_p, CLK_CON_MUX_CLK_CPUCL1, 12, 1, CLK_STAT_MUX_CLK_CPUCL1, 12, 2, CLK_CON_MUX_CLK_CPUCL1, 21, 0);
CLK_MUX(DISPAUD_MUX_DISP_PLL, dispaud_mux_disp_pll_p, CLK_CON_MUX_DISP_PLL, 12, 1, CLK_STAT_MUX_DISP_PLL, 12, 2, CLK_CON_MUX_DISP_PLL, 21, 0);
CLK_MUX(DISPAUD_MUX_AUD_PLL, dispaud_mux_aud_pll_p, CLK_CON_MUX_AUD_PLL, 12, 1, CLK_STAT_MUX_AUD_PLL, 12, 2, CLK_CON_MUX_AUD_PLL, 21, 0);
CLK_MUX(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, dispaud_mux_clkcmu_dispaud_bus_user_p, CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER, 12, 1, CLK_STAT_MUX_CLKCMU_DISPAUD_BUS_USER, 12, 2, CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER, 21, 0);
CLK_MUX(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, dispaud_mux_clkcmu_dispaud_decon_int_vclk_user_p, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, 12, 1, CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, 12, 2, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, 21, 0);
CLK_MUX(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, dispaud_mux_clkcmu_dispaud_decon_int_eclk_user_p, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, 12, 1, CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, 12, 2, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, 21, 0);
CLK_MUX(DISPAUD_MUX_CLK_DISPAUD_DECON_INT_VCLK, dispaud_mux_clk_dispaud_decon_int_vclk_p, CLK_CON_MUX_CLK_DISPAUD_DECON_INT_VCLK, 12, 1, CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_VCLK, 12, 2, CLK_CON_MUX_CLK_DISPAUD_DECON_INT_VCLK, 21, 0);
CLK_MUX(DISPAUD_MUX_CLK_DISPAUD_DECON_INT_ECLK, dispaud_mux_clk_dispaud_decon_int_eclk_p, CLK_CON_MUX_CLK_DISPAUD_DECON_INT_ECLK, 12, 1, CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_ECLK, 12, 2, CLK_CON_MUX_CLK_DISPAUD_DECON_INT_ECLK, 21, 0);
CLK_MUX(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, dispaud_mux_clkphy_dispaud_mipiphy_txbyteclkhs_user_p, CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 12, 1, CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 12, 2, CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 21, 0);
CLK_MUX(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, dispaud_mux_clkphy_dispaud_mipiphy_rxclkesc0_user_p, CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 12, 1, CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 12, 2, CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 21, 0);
CLK_MUX(DISPAUD_MUX_CLK_DISPAUD_MI2S, dispaud_mux_clk_dispaud_mi2s_p, CLK_CON_MUX_CLK_DISPAUD_MI2S, 12, 1, NULL, 12, 1, CLK_CON_MUX_CLK_DISPAUD_MI2S, 21, 0);
CLK_MUX(FSYS_MUX_USB_PLL, fsys_mux_usb_pll_p, CLK_CON_MUX_USB_PLL, 12, 1, CLK_STAT_MUX_USB_PLL, 12, 2, CLK_CON_MUX_USB_PLL, 21, 0);
CLK_MUX(FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, fsys_mux_clkphy_fsys_usb20drd_phyclock_user_p, CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 12, 1, CLK_STAT_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 12, 2, CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 21, 0);
CLK_MUX(FSYS_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER, fsys_mux_clkphy_fsys_ufs_tx0_symbol_user_p, CLK_CON_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER, 12, 1, CLK_STAT_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER, 12, 2, CLK_CON_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER, 21, 0);
CLK_MUX(FSYS_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER, fsys_mux_clkphy_fsys_ufs_rx0_symbol_user_p, CLK_CON_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER, 12, 1, CLK_STAT_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER, 12, 2, CLK_CON_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER, 21, 0);
CLK_MUX(G3D_MUX_G3D_PLL, g3d_mux_g3d_pll_p, CLK_CON_MUX_G3D_PLL, 12, 1, CLK_STAT_MUX_G3D_PLL, 12, 2, CLK_CON_MUX_G3D_PLL, 21, 0);
CLK_MUX(G3D_MUX_CLKCMU_G3D_SWITCH_USER, g3d_mux_clkcmu_g3d_switch_user_p, CLK_CON_MUX_CLKCMU_G3D_SWITCH_USER, 12, 1, CLK_STAT_MUX_CLKCMU_G3D_SWITCH_USER, 12, 2, CLK_CON_MUX_CLKCMU_G3D_SWITCH_USER, 21, 0);
CLK_MUX(G3D_MUX_CLK_G3D, g3d_mux_clk_g3d_p, CLK_CON_MUX_CLK_G3D, 12, 1, CLK_STAT_MUX_CLK_G3D, 12, 2, CLK_CON_MUX_CLK_G3D, 21, 0);
CLK_MUX(ISP_MUX_ISP_PLL, isp_mux_isp_pll_p, CLK_CON_MUX_ISP_PLL, 12, 1, CLK_STAT_MUX_ISP_PLL, 12, 2, CLK_CON_MUX_ISP_PLL, 21, 0);
CLK_MUX(ISP_MUX_CLKCMU_ISP_VRA_USER, isp_mux_clkcmu_isp_vra_user_p, CLK_CON_MUX_CLKCMU_ISP_VRA_USER, 12, 1, CLK_STAT_MUX_CLKCMU_ISP_VRA_USER, 12, 2, CLK_CON_MUX_CLKCMU_ISP_VRA_USER, 21, 0);
CLK_MUX(ISP_MUX_CLKCMU_ISP_CAM_USER, isp_mux_clkcmu_isp_cam_user_p, CLK_CON_MUX_CLKCMU_ISP_CAM_USER, 12, 1, CLK_STAT_MUX_CLKCMU_ISP_CAM_USER, 12, 2, CLK_CON_MUX_CLKCMU_ISP_CAM_USER, 21, 0);
CLK_MUX(ISP_MUX_CLKCMU_ISP_ISP_USER, isp_mux_clkcmu_isp_isp_user_p, CLK_CON_MUX_CLKCMU_ISP_ISP_USER, 12, 1, CLK_STAT_MUX_CLKCMU_ISP_ISP_USER, 12, 2, CLK_CON_MUX_CLKCMU_ISP_ISP_USER, 21, 0);
CLK_MUX(ISP_MUX_CLK_ISP_VRA, isp_mux_clk_isp_vra_p, CLK_CON_MUX_CLK_ISP_VRA, 12, 1, CLK_STAT_MUX_CLK_ISP_VRA, 12, 2, CLK_CON_MUX_CLK_ISP_VRA, 21, 0);
CLK_MUX(ISP_MUX_CLK_ISP_CAM, isp_mux_clk_isp_cam_p, CLK_CON_MUX_CLK_ISP_CAM, 12, 1, CLK_STAT_MUX_CLK_ISP_CAM, 12, 2, CLK_CON_MUX_CLK_ISP_CAM, 21, 0);
CLK_MUX(ISP_MUX_CLK_ISP_ISP, isp_mux_clk_isp_isp_p, CLK_CON_MUX_CLK_ISP_ISP, 12, 1, CLK_STAT_MUX_CLK_ISP_ISP, 12, 2, CLK_CON_MUX_CLK_ISP_ISP, 21, 0);
CLK_MUX(ISP_MUX_CLK_ISP_ISPD, isp_mux_clk_isp_ispd_p, CLK_CON_MUX_CLK_ISP_ISPD, 12, 1, CLK_STAT_MUX_CLK_ISP_ISPD, 12, 2, CLK_CON_MUX_CLK_ISP_ISPD, 21, 0);
CLK_MUX(ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, isp_mux_clkphy_isp_s_rxbyteclkhs0_s4_user_p, CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 12, 1, CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 12, 2, CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 21, 0);
CLK_MUX(ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, isp_mux_clkphy_isp_s_rxbyteclkhs0_s4s_user_p, CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 12, 1, CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 12, 2, CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 21, 0);
CLK_MUX(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, mfcmscl_mux_clkcmu_mfcmscl_mscl_user_p, CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER, 12, 1, CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL_USER, 12, 2, CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER, 21, 0);
CLK_MUX(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER, mfcmscl_mux_clkcmu_mfcmscl_mfc_user_p, CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER, 12, 1, CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC_USER, 12, 2, CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER, 21, 0);
CLK_MUX(MIF_MUX_MEM_PLL, mif_mux_mem_pll_p, CLK_CON_MUX_MEM_PLL, 12, 1, CLK_STAT_MUX_MEM_PLL, 12, 2, CLK_CON_MUX_MEM_PLL, 21, 0);
CLK_MUX(MIF_MUX_MEDIA_PLL, mif_mux_media_pll_p, CLK_CON_MUX_MEDIA_PLL, 12, 1, CLK_STAT_MUX_MEDIA_PLL, 12, 2, CLK_CON_MUX_MEDIA_PLL, 21, 0);
CLK_MUX(MIF_MUX_BUS_PLL, mif_mux_bus_pll_p, CLK_CON_MUX_BUS_PLL, 12, 1, CLK_STAT_MUX_BUS_PLL, 12, 2, CLK_CON_MUX_BUS_PLL, 21, 0);
CLK_MUX(MIF_MUX_CLK_MIF_PHY_CLK2X, mif_mux_clk_mif_phy_clk2x_p, CLK_CON_MUX_CLK_MIF_PHY_CLK2X, 12, 1, CLK_STAT_MUX_CLK_MIF_PHY_CLK2X, 12, 2, CLK_CON_MUX_CLK_MIF_PHY_CLK2X, 21, 0);
CLK_MUX(MIF_MUX_CLK_MIF_PHY_SWITCH, mif_mux_clk_mif_phy_switch_p, CLK_CON_MUX_CLK_MIF_PHY_SWITCH, 12, 1, CLK_STAT_MUX_CLK_MIF_PHY_SWITCH, 12, 2, CLK_CON_MUX_CLK_MIF_PHY_SWITCH, 21, 0);
CLK_MUX(MIF_MUX_CLK_MIF_BUSD, mif_mux_clk_mif_busd_p, CLK_CON_MUX_CLK_MIF_BUSD, 12, 2, CLK_STAT_MUX_CLK_MIF_BUSD, 12, 4, CLK_CON_MUX_CLK_MIF_BUSD, 21, 0);
CLK_MUX(MIF_MUX_CLK_MIF_CCI, mif_mux_clk_mif_cci_p, CLK_CON_MUX_CLK_MIF_CCI, 12, 2, CLK_STAT_MUX_CLK_MIF_CCI, 12, 4, CLK_CON_MUX_CLK_MIF_CCI, 21, 0);
CLK_MUX(MIF_MUX_CLKCMU_ISP_VRA,	mif_mux_clkcmu_isp_vra_p,	CLK_CON_MUX_CLKCMU_ISP_VRA,	12,	2,	CLK_STAT_MUX_CLKCMU_ISP_VRA,	12,	4,	CLK_CON_MUX_CLKCMU_ISP_VRA,	21,	MIF_MUXGATE_CLKCMU_ISP_VRA);
CLK_MUX(MIF_MUX_CLKCMU_ISP_CAM,	mif_mux_clkcmu_isp_cam_p,	CLK_CON_MUX_CLKCMU_ISP_CAM,	12,	1,	CLK_STAT_MUX_CLKCMU_ISP_CAM,	12,	2,	CLK_CON_MUX_CLKCMU_ISP_CAM,	21,	MIF_MUXGATE_CLKCMU_ISP_CAM);
CLK_MUX(MIF_MUX_CLKCMU_ISP_ISP,	mif_mux_clkcmu_isp_isp_p,	CLK_CON_MUX_CLKCMU_ISP_ISP,	12,	1,	CLK_STAT_MUX_CLKCMU_ISP_ISP,	12,	2,	CLK_CON_MUX_CLKCMU_ISP_ISP,	21,	MIF_MUXGATE_CLKCMU_ISP_ISP);
CLK_MUX(MIF_MUX_CLKCMU_DISPAUD_BUS,	mif_mux_clkcmu_dispaud_bus_p,	CLK_CON_MUX_CLKCMU_DISPAUD_BUS,	12,	1,	CLK_STAT_MUX_CLKCMU_DISPAUD_BUS,	12,	2,	CLK_CON_MUX_CLKCMU_DISPAUD_BUS,	21,	MIF_MUXGATE_CLKCMU_DISPAUD_BUS);
CLK_MUX(MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK,	mif_mux_clkcmu_dispaud_decon_int_vclk_p,	CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK,	12,	1,	CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK,	12,	2,	CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK,	21,	MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK);
CLK_MUX(MIF_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK,	mif_mux_clkcmu_dispaud_decon_int_eclk_p,	CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK,	12,	1,	CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK,	12,	2,	CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK,	21,	MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_ECLK);
CLK_MUX(MIF_MUX_CLKCMU_MFCMSCL_MSCL,	mif_mux_clkcmu_mfcmscl_mscl_p,	CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL,	12,	2,	CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL,	12,	4,	CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL,	21,	MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL);
CLK_MUX(MIF_MUX_CLKCMU_MFCMSCL_MFC,	mif_mux_clkcmu_mfcmscl_mfc_p,	CLK_CON_MUX_CLKCMU_MFCMSCL_MFC,	12,	2,	CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC,	12,	4,	CLK_CON_MUX_CLKCMU_MFCMSCL_MFC,	21,	MIF_MUXGATE_CLKCMU_MFCMSCL_MFC);
CLK_MUX(MIF_MUX_CLKCMU_FSYS_BUS,	mif_mux_clkcmu_fsys_bus_p,	CLK_CON_MUX_CLKCMU_FSYS_BUS,	12,	1,	CLK_STAT_MUX_CLKCMU_FSYS_BUS,	12,	2,	CLK_CON_MUX_CLKCMU_FSYS_BUS,	21,	0);
CLK_MUX(MIF_MUX_CLKCMU_FSYS_MMC0,	mif_mux_clkcmu_fsys_mmc0_p,	CLK_CON_MUX_CLKCMU_FSYS_MMC0,	12,	1,	CLK_STAT_MUX_CLKCMU_FSYS_MMC0,	12,	2,	CLK_CON_MUX_CLKCMU_FSYS_MMC0,	21,	MIF_MUXGATE_CLKCMU_FSYS_MMC0);
CLK_MUX(MIF_MUX_CLKCMU_FSYS_MMC1,	mif_mux_clkcmu_fsys_mmc1_p,	CLK_CON_MUX_CLKCMU_FSYS_MMC1,	12,	1,	CLK_STAT_MUX_CLKCMU_FSYS_MMC1,	12,	2,	CLK_CON_MUX_CLKCMU_FSYS_MMC1,	21,	MIF_MUXGATE_CLKCMU_FSYS_MMC1);
CLK_MUX(MIF_MUX_CLKCMU_FSYS_MMC2,	mif_mux_clkcmu_fsys_mmc2_p,	CLK_CON_MUX_CLKCMU_FSYS_MMC2,	12,	1,	CLK_STAT_MUX_CLKCMU_FSYS_MMC2,	12,	2,	CLK_CON_MUX_CLKCMU_FSYS_MMC2,	21,	MIF_MUXGATE_CLKCMU_FSYS_MMC2);
CLK_MUX(MIF_MUX_CLKCMU_FSYS_UFSUNIPRO,	mif_mux_clkcmu_fsys_ufsunipro_p,	CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO,	12,	1,	CLK_STAT_MUX_CLKCMU_FSYS_UFSUNIPRO,	12,	2,	CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO,	21,	MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO);
CLK_MUX(MIF_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG,	mif_mux_clkcmu_fsys_ufsunipro_cfg_p,	CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG,	12,	1,	CLK_STAT_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG,	12,	2,	CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG,	21,	MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO_CFG);
CLK_MUX(MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK,	mif_mux_clkcmu_fsys_usb20drd_refclk_p,	CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK,	12,	1,	CLK_STAT_MUX_CLKCMU_FSYS_USB20DRD_REFCLK,	12,	2,	CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK,	21,	MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK);
CLK_MUX(MIF_MUX_CLKCMU_PERI_BUS,	mif_mux_clkcmu_peri_bus_p,	CLK_CON_MUX_CLKCMU_PERI_BUS,	12,	1,	CLK_STAT_MUX_CLKCMU_PERI_BUS,	12,	2,	CLK_CON_MUX_CLKCMU_PERI_BUS,	21,	0);
CLK_MUX(MIF_MUX_CLKCMU_PERI_UART_BTWIFIFM,	mif_mux_clkcmu_peri_uart_btwififm_p,	CLK_CON_MUX_CLKCMU_PERI_UART_BTWIFIFM,	12,	1,	CLK_STAT_MUX_CLKCMU_PERI_UART_BTWIFIFM,	12,	2,	CLK_CON_MUX_CLKCMU_PERI_UART_BTWIFIFM,	21,	MIF_MUXGATE_CLKCMU_PERI_UART_BTWIFIFM);
CLK_MUX(MIF_MUX_CLKCMU_PERI_UART_DEBUG,	mif_mux_clkcmu_peri_uart_debug_p,	CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG,	12,	1,	CLK_STAT_MUX_CLKCMU_PERI_UART_DEBUG,	12,	2,	CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG,	21,	MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG);
CLK_MUX(MIF_MUX_CLKCMU_PERI_UART_SENSOR,	mif_mux_clkcmu_peri_uart_sensor_p,	CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR,	12,	1,	CLK_STAT_MUX_CLKCMU_PERI_UART_SENSOR,	12,	2,	CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR,	21,	MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR);
CLK_MUX(MIF_MUX_CLKCMU_PERI_SPI_FRONTFROM,	mif_mux_clkcmu_peri_spi_frontfrom_p,	CLK_CON_MUX_CLKCMU_PERI_SPI_FRONTFROM,	12,	1,	CLK_STAT_MUX_CLKCMU_PERI_SPI_FRONTFROM,	12,	2,	CLK_CON_MUX_CLKCMU_PERI_SPI_FRONTFROM,	21,	MIF_MUXGATE_CLKCMU_PERI_SPI_FRONTFROM);
CLK_MUX(MIF_MUX_CLKCMU_PERI_SPI_REARFROM,	mif_mux_clkcmu_peri_spi_rearfrom_p,	CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM,	12,	1,	CLK_STAT_MUX_CLKCMU_PERI_SPI_REARFROM,	12,	2,	CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM,	21,	MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM);
CLK_MUX(MIF_MUX_CLKCMU_PERI_SPI_ESE,	mif_mux_clkcmu_peri_spi_ese_p,	CLK_CON_MUX_CLKCMU_PERI_SPI_ESE,	12,	1,	CLK_STAT_MUX_CLKCMU_PERI_SPI_ESE,	12,	2,	CLK_CON_MUX_CLKCMU_PERI_SPI_ESE,	21,	MIF_MUXGATE_CLKCMU_PERI_SPI_ESE);
CLK_MUX(MIF_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR,	mif_mux_clkcmu_peri_spi_voiceprocessor_p,	CLK_CON_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR,	12,	1,	CLK_STAT_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR,	12,	2,	CLK_CON_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR,	21,	MIF_MUXGATE_CLKCMU_PERI_SPI_VOICEPROCESSOR);
CLK_MUX(MIF_MUX_CLKCMU_PERI_SPI_SENSORHUB,	mif_mux_clkcmu_peri_spi_sensorhub_p,	CLK_CON_MUX_CLKCMU_PERI_SPI_SENSORHUB,	12,	1,	CLK_STAT_MUX_CLKCMU_PERI_SPI_SENSORHUB,	12,	2,	CLK_CON_MUX_CLKCMU_PERI_SPI_SENSORHUB,	21,	MIF_MUXGATE_CLKCMU_PERI_SPI_SENSORHUB);
CLK_MUX(MIF_MUX_CLKCMU_ISP_SENSOR0,	mif_mux_clkcmu_isp_sensor0_p,	CLK_CON_MUX_CLKCMU_ISP_SENSOR0,	12,	1,	CLK_STAT_MUX_CLKCMU_ISP_SENSOR0,	12,	2,	CLK_CON_MUX_CLKCMU_ISP_SENSOR0,	21,	MIF_MUXGATE_CLKCMU_ISP_SENSOR0);
CLK_MUX(MIF_MUX_CLKCMU_ISP_SENSOR1,	mif_mux_clkcmu_isp_sensor1_p,	CLK_CON_MUX_CLKCMU_ISP_SENSOR1,	12,	1,	CLK_STAT_MUX_CLKCMU_ISP_SENSOR1,	12,	2,	CLK_CON_MUX_CLKCMU_ISP_SENSOR1,	21,	MIF_MUXGATE_CLKCMU_ISP_SENSOR1);
CLK_MUX(MIF_MUX_CLKCMU_ISP_SENSOR2,	mif_mux_clkcmu_isp_sensor2_p,	CLK_CON_MUX_CLKCMU_ISP_SENSOR2,	12,	1,	CLK_STAT_MUX_CLKCMU_ISP_SENSOR2,	12,	2,	CLK_CON_MUX_CLKCMU_ISP_SENSOR2,	21,	MIF_MUXGATE_CLKCMU_ISP_SENSOR2);


CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_1, CPUCL0_MUX_CLK_CPUCL0, CLK_CON_DIV_CLK_CPUCL0_1, 0, 3, CLK_CON_DIV_CLK_CPUCL0_1, 25, 1, 0);
CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_2, CPUCL0_DIV_CLK_CPUCL0_1, CLK_CON_DIV_CLK_CPUCL0_2, 0, 3, CLK_CON_DIV_CLK_CPUCL0_2, 25, 1, 0);
CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_ACLK, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_ACLK, 0, 3, CLK_CON_DIV_CLK_CPUCL0_ACLK, 25, 1, 0);
CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_PCLK, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_PCLK, 0, 3, CLK_CON_DIV_CLK_CPUCL0_PCLK, 25, 1, 0);
CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_ATCLK, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_ATCLK, 0, 3, CLK_CON_DIV_CLK_CPUCL0_ATCLK, 25, 1, 0);
CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_PCLKDBG, 0, 3, CLK_CON_DIV_CLK_CPUCL0_PCLKDBG, 25, 1, 0);
CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_CNTCLK, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_CNTCLK, 0, 3, CLK_CON_DIV_CLK_CPUCL0_CNTCLK, 25, 1, 0);
CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_RUN_MONITOR, 0, 3, CLK_CON_DIV_CLK_CPUCL0_RUN_MONITOR, 25, 1, 0);
CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_HPM, CPUCL0_MUX_CLK_CPUCL0, CLK_CON_DIV_CLK_CPUCL0_HPM, 0, 3, CLK_CON_DIV_CLK_CPUCL0_HPM, 25, 1, 0);
CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_PLL, CPUCL0_MUX_CLK_CPUCL0, CLK_CON_DIV_CLK_CPUCL0_PLL, 0, 3, CLK_CON_DIV_CLK_CPUCL0_PLL, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_1, CPUCL1_MUX_CLK_CPUCL1, CLK_CON_DIV_CLK_CPUCL1_1, 0, 3, CLK_CON_DIV_CLK_CPUCL1_1, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_2, CPUCL1_DIV_CLK_CPUCL1_1, CLK_CON_DIV_CLK_CPUCL1_2, 0, 3, CLK_CON_DIV_CLK_CPUCL1_2, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_ACLK, CPUCL1_DIV_CLK_CPUCL1_2, CLK_CON_DIV_CLK_CPUCL1_ACLK, 0, 3, CLK_CON_DIV_CLK_CPUCL1_ACLK, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_PCLK, CPUCL1_DIV_CLK_CPUCL1_2, CLK_CON_DIV_CLK_CPUCL1_PCLK, 0, 3, CLK_CON_DIV_CLK_CPUCL1_PCLK, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_ATCLK, CPUCL1_DIV_CLK_CPUCL1_2, CLK_CON_DIV_CLK_CPUCL1_ATCLK, 0, 3, CLK_CON_DIV_CLK_CPUCL1_ATCLK, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_PCLKDBG, CPUCL1_DIV_CLK_CPUCL1_2, CLK_CON_DIV_CLK_CPUCL1_PCLKDBG, 0, 3, CLK_CON_DIV_CLK_CPUCL1_PCLKDBG, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_CNTCLK, CPUCL1_DIV_CLK_CPUCL1_2, CLK_CON_DIV_CLK_CPUCL1_CNTCLK, 0, 3, CLK_CON_DIV_CLK_CPUCL1_CNTCLK, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_RUN_MONITOR, CPUCL1_DIV_CLK_CPUCL1_2, CLK_CON_DIV_CLK_CPUCL1_RUN_MONITOR, 0, 3, CLK_CON_DIV_CLK_CPUCL1_RUN_MONITOR, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_HPM, CPUCL1_MUX_CLK_CPUCL1, CLK_CON_DIV_CLK_CPUCL1_HPM, 0, 3, CLK_CON_DIV_CLK_CPUCL1_HPM, 25, 1, 0);
CLK_DIV(CPUCL1_DIV_CLK_CPUCL1_PLL, CPUCL1_MUX_CLK_CPUCL1, CLK_CON_DIV_CLK_CPUCL1_PLL, 0, 3, CLK_CON_DIV_CLK_CPUCL1_PLL, 25, 1, 0);
CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_APB, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_DIV_CLK_DISPAUD_APB, 0, 2, CLK_CON_DIV_CLK_DISPAUD_APB, 25, 1, 0);
CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK, DISPAUD_MUX_CLK_DISPAUD_DECON_INT_VCLK, CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK, 0, 3, CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK, 25, 1, 0);
CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK, DISPAUD_MUX_CLK_DISPAUD_DECON_INT_ECLK, CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK, 0, 3, CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK, 25, 1, 0);
CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_MI2S, DISPAUD_MUX_CLK_DISPAUD_MI2S, CLK_CON_DIV_CLK_DISPAUD_MI2S, 0, 4, CLK_CON_DIV_CLK_DISPAUD_MI2S, 25, 1, 0);
CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_MIXER, DISPAUD_MUX_AUD_PLL, CLK_CON_DIV_CLK_DISPAUD_MIXER, 0, 4, CLK_CON_DIV_CLK_DISPAUD_MIXER, 25, 1, 0);
CLK_DIV(G3D_DIV_CLK_G3D_BUS, G3D_MUX_CLK_G3D, CLK_CON_DIV_CLK_G3D_BUS, 0, 3, CLK_CON_DIV_CLK_G3D_BUS, 25, 1, 0);
CLK_DIV(G3D_DIV_CLK_G3D_APB, G3D_DIV_CLK_G3D_BUS, CLK_CON_DIV_CLK_G3D_APB, 0, 3, CLK_CON_DIV_CLK_G3D_APB, 25, 1, 0);
CLK_DIV(ISP_DIV_CLK_ISP_APB, ISP_MUX_CLK_ISP_VRA, CLK_CON_DIV_CLK_ISP_APB, 0, 2, CLK_CON_DIV_CLK_ISP_APB, 25, 1, 0);
CLK_DIV(ISP_DIV_CLK_ISP_CAM_HALF, ISP_MUX_CLK_ISP_CAM, CLK_CON_DIV_CLK_ISP_CAM_HALF, 0, 2, CLK_CON_DIV_CLK_ISP_CAM_HALF, 25, 1, 0);
CLK_DIV(MFCMSCL_DIV_CLK_MFCMSCL_APB, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_DIV_CLK_MFCMSCL_APB, 0, 2, CLK_CON_DIV_CLK_MFCMSCL_APB, 25, 1, 0);
CLK_DIV(MIF_DIV_CLK_MIF_PHY_CLKM, MIF_MUX_CLK_MIF_PHY_CLK2X, CLK_CON_DIV_CLK_MIF_PHY_CLKM, 0, 2, CLK_CON_DIV_CLK_MIF_PHY_CLKM, 25, 1, 0);
CLK_DIV(MIF_DIV_CLK_MIF_BUSD, MIF_MUX_CLK_MIF_BUSD, CLK_CON_DIV_CLK_MIF_BUSD, 0, 4, CLK_CON_DIV_CLK_MIF_BUSD, 25, 1, 0);
CLK_DIV(MIF_DIV_CLK_MIF_APB, MIF_DIV_CLK_MIF_BUSD, CLK_CON_DIV_CLK_MIF_APB, 0, 2, CLK_CON_DIV_CLK_MIF_APB, 25, 1, 0);
CLK_DIV(MIF_DIV_CLK_MIF_CCI, MIF_MUX_CLK_MIF_CCI, CLK_CON_DIV_CLK_MIF_CCI, 0, 4, CLK_CON_DIV_CLK_MIF_CCI, 25, 1, 0);
CLK_DIV(MIF_DIV_CLK_MIF_BUSP, MIF_DIV_CLK_MIF_CCI, CLK_CON_DIV_CLK_MIF_BUSP, 0, 2, CLK_CON_DIV_CLK_MIF_BUSP, 25, 1, 0);
CLK_DIV(MIF_DIV_CLK_MIF_HSI2C, MIF_FF_MUX_MEDIA_PLL_DIV2, CLK_CON_DIV_CLK_MIF_HSI2C, 0, 4, CLK_CON_DIV_CLK_MIF_HSI2C, 25, 1, 0);
CLK_DIV(MIF_DIV_CLKCMU_CP_MEDIA_PLL, MIF_MUX_MEDIA_PLL, CLK_CON_DIV_CLKCMU_CP_MEDIA_PLL, 0, 4, CLK_CON_DIV_CLKCMU_CP_MEDIA_PLL, 25, 1, 0);
CLK_DIV(MIF_DIV_CLKCMU_CPUCL0_SWITCH, MIF_FF_MUX_BUS_PLL_DIV2, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 2, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 25, 1, 0);
CLK_DIV(MIF_DIV_CLKCMU_CPUCL1_SWITCH, MIF_FF_MUX_BUS_PLL_DIV2, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 2, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 25, 1, 0);
CLK_DIV(MIF_DIV_CLKCMU_G3D_SWITCH, MIF_FF_MUX_BUS_PLL_DIV2, CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 2, CLK_CON_DIV_CLKCMU_G3D_SWITCH, 25, 1, 0);
CLK_DIV(MIF_DIV_CLKCMU_ISP_VRA,	MIF_MUX_CLKCMU_ISP_VRA,	CLK_CON_DIV_CLKCMU_ISP_VRA,	0,	4,	CLK_CON_DIV_CLKCMU_ISP_VRA,	25,	1,	MIF_MUXGATE_CLKCMU_ISP_VRA);
CLK_DIV(MIF_DIV_CLKCMU_ISP_CAM,	MIF_MUX_CLKCMU_ISP_CAM,	CLK_CON_DIV_CLKCMU_ISP_CAM,	0,	4,	CLK_CON_DIV_CLKCMU_ISP_CAM,	25,	1,	MIF_MUXGATE_CLKCMU_ISP_CAM);
CLK_DIV(MIF_DIV_CLKCMU_ISP_ISP,	MIF_MUX_CLKCMU_ISP_ISP,	CLK_CON_DIV_CLKCMU_ISP_ISP,	0,	4,	CLK_CON_DIV_CLKCMU_ISP_ISP,	25,	1,	MIF_MUXGATE_CLKCMU_ISP_ISP);
CLK_DIV(MIF_DIV_CLKCMU_DISPAUD_BUS,	MIF_MUX_CLKCMU_DISPAUD_BUS,	CLK_CON_DIV_CLKCMU_DISPAUD_BUS,	0,	4,	CLK_CON_DIV_CLKCMU_DISPAUD_BUS,	25,	1,	MIF_MUXGATE_CLKCMU_DISPAUD_BUS);
CLK_DIV(MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK,	MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK,	CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK,	0,	4,	CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK,	25,	1,	MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK);
CLK_DIV(MIF_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK,	MIF_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK,	CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK,	0,	4,	CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK,	25,	1,	MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_ECLK);
CLK_DIV(MIF_DIV_CLKCMU_MFCMSCL_MSCL,	MIF_MUX_CLKCMU_MFCMSCL_MSCL,	CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL,	0,	4,	CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL,	25,	1,	MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL);
CLK_DIV(MIF_DIV_CLKCMU_MFCMSCL_MFC,	MIF_MUX_CLKCMU_MFCMSCL_MFC,	CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,	0,	4,	CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,	25,	1,	MIF_MUXGATE_CLKCMU_MFCMSCL_MFC);
CLK_DIV(MIF_DIV_CLKCMU_FSYS_BUS,	MIF_MUX_CLKCMU_FSYS_BUS,	CLK_CON_DIV_CLKCMU_FSYS_BUS,	0,	4,	CLK_CON_DIV_CLKCMU_FSYS_BUS,	25,	1,	0);
CLK_DIV(MIF_DIV_CLKCMU_FSYS_MMC0,	MIF_MUX_CLKCMU_FSYS_MMC0,	CLK_CON_DIV_CLKCMU_FSYS_MMC0,	0,	10,	CLK_CON_DIV_CLKCMU_FSYS_MMC0,	25,	1,	MIF_MUXGATE_CLKCMU_FSYS_MMC0);
CLK_DIV(MIF_DIV_CLKCMU_FSYS_MMC1,	MIF_MUX_CLKCMU_FSYS_MMC1,	CLK_CON_DIV_CLKCMU_FSYS_MMC1,	0,	10,	CLK_CON_DIV_CLKCMU_FSYS_MMC1,	25,	1,	MIF_MUXGATE_CLKCMU_FSYS_MMC1);
CLK_DIV(MIF_DIV_CLKCMU_FSYS_MMC2,	MIF_MUX_CLKCMU_FSYS_MMC2,	CLK_CON_DIV_CLKCMU_FSYS_MMC2,	0,	10,	CLK_CON_DIV_CLKCMU_FSYS_MMC2,	25,	1,	MIF_MUXGATE_CLKCMU_FSYS_MMC2);
CLK_DIV(MIF_DIV_CLKCMU_FSYS_UFSUNIPRO,	MIF_MUX_CLKCMU_FSYS_UFSUNIPRO,	CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO,	0,	4,	CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO,	25,	1,	MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO);
CLK_DIV(MIF_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG,	MIF_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG,	CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG,	0,	4,	CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG,	25,	1,	MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO_CFG);
CLK_DIV(MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK,	MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK,	CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK,	0,	4,	CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK,	25,	1,	MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK);
CLK_DIV(MIF_DIV_CLKCMU_PERI_BUS,	MIF_MUX_CLKCMU_PERI_BUS,	CLK_CON_DIV_CLKCMU_PERI_BUS,	0,	4,	CLK_CON_DIV_CLKCMU_PERI_BUS,	25,	1,	0);
CLK_DIV(MIF_DIV_CLKCMU_PERI_UART_BTWIFIFM,	MIF_MUX_CLKCMU_PERI_UART_BTWIFIFM,	CLK_CON_DIV_CLKCMU_PERI_UART_BTWIFIFM,	0,	4,	CLK_CON_DIV_CLKCMU_PERI_UART_BTWIFIFM,	25,	1,	MIF_MUXGATE_CLKCMU_PERI_UART_BTWIFIFM);
CLK_DIV(MIF_DIV_CLKCMU_PERI_UART_DEBUG,	MIF_MUX_CLKCMU_PERI_UART_DEBUG,	CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG,	0,	4,	CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG,	25,	1,	MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG);
CLK_DIV(MIF_DIV_CLKCMU_PERI_UART_SENSOR,	MIF_MUX_CLKCMU_PERI_UART_SENSOR,	CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR,	0,	4,	CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR,	25,	1,	MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR);
CLK_DIV(MIF_DIV_CLKCMU_PERI_SPI_FRONTFROM,	MIF_MUX_CLKCMU_PERI_SPI_FRONTFROM,	CLK_CON_DIV_CLKCMU_PERI_SPI_FRONTFROM,	0,	6,	CLK_CON_DIV_CLKCMU_PERI_SPI_FRONTFROM,	25,	1,	MIF_MUXGATE_CLKCMU_PERI_SPI_FRONTFROM);
CLK_DIV(MIF_DIV_CLKCMU_PERI_SPI_REARFROM,	MIF_MUX_CLKCMU_PERI_SPI_REARFROM,	CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM,	0,	6,	CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM,	25,	1,	MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM);
CLK_DIV(MIF_DIV_CLKCMU_PERI_SPI_ESE,	MIF_MUX_CLKCMU_PERI_SPI_ESE,	CLK_CON_DIV_CLKCMU_PERI_SPI_ESE,	0,	6,	CLK_CON_DIV_CLKCMU_PERI_SPI_ESE,	25,	1,	MIF_MUXGATE_CLKCMU_PERI_SPI_ESE);
CLK_DIV(MIF_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR,	MIF_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR,	CLK_CON_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR,	0,	6,	CLK_CON_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR,	25,	1,	MIF_MUXGATE_CLKCMU_PERI_SPI_VOICEPROCESSOR);
CLK_DIV(MIF_DIV_CLKCMU_PERI_SPI_SENSORHUB,	MIF_MUX_CLKCMU_PERI_SPI_SENSORHUB,	CLK_CON_DIV_CLKCMU_PERI_SPI_SENSORHUB,	0,	6,	CLK_CON_DIV_CLKCMU_PERI_SPI_SENSORHUB,	25,	1,	MIF_MUXGATE_CLKCMU_PERI_SPI_SENSORHUB);
CLK_DIV(MIF_DIV_CLKCMU_ISP_SENSOR0,	MIF_MUX_CLKCMU_ISP_SENSOR0,	CLK_CON_DIV_CLKCMU_ISP_SENSOR0,	0,	6,	CLK_CON_DIV_CLKCMU_ISP_SENSOR0,	25,	1,	MIF_MUXGATE_CLKCMU_ISP_SENSOR0);
CLK_DIV(MIF_DIV_CLKCMU_ISP_SENSOR1,	MIF_MUX_CLKCMU_ISP_SENSOR1,	CLK_CON_DIV_CLKCMU_ISP_SENSOR1,	0,	6,	CLK_CON_DIV_CLKCMU_ISP_SENSOR1,	25,	1,	MIF_MUXGATE_CLKCMU_ISP_SENSOR1);
CLK_DIV(MIF_DIV_CLKCMU_ISP_SENSOR2,	MIF_MUX_CLKCMU_ISP_SENSOR2,	CLK_CON_DIV_CLKCMU_ISP_SENSOR2,	0,	6,	CLK_CON_DIV_CLKCMU_ISP_SENSOR2,	25,	1,	MIF_MUXGATE_CLKCMU_ISP_SENSOR2);



CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK, OSCCLK, CLK_ENABLE_CLK_CPUCL0_OSCCLK, 1);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0, OSCCLK, CLK_ENABLE_CLK_CPUCL0_OSCCLK, 0);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK, CPUCL0_DIV_CLK_CPUCL0_ACLK, CLK_ENABLE_CLK_CPUCL0_ACLK, 0);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 5);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 4);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 3);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 2);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 1);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 0);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK, CPUCL0_DIV_CLK_CPUCL0_ATCLK, CLK_ENABLE_CLK_CPUCL0_ATCLK, 0);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 6);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 5);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 4);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 3);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 2);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 1);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 0);
CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C, CPUCL0_DIV_CLK_CPUCL0_HPM, CLK_ENABLE_CLK_CPUCL0_HPM, 0);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_CLK, OSCCLK, CLK_ENABLE_CLK_CPUCL1_OSCCLK, 1);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_I_CLK__PMU_CPUCL1, OSCCLK, CLK_ENABLE_CLK_CPUCL1_OSCCLK, 0);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCS_D_CPUCL1_IPCLKPORT_I_CLK, CPUCL1_DIV_CLK_CPUCL1_ACLK, CLK_ENABLE_CLK_CPUCL1_ACLK, 0);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, CPUCL1_DIV_CLK_CPUCL1_PCLK, CLK_ENABLE_CLK_CPUCL1_PCLK, 5);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_PCLK, CPUCL1_DIV_CLK_CPUCL1_PCLK, CLK_ENABLE_CLK_CPUCL1_PCLK, 4);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_I_PCLK, CPUCL1_DIV_CLK_CPUCL1_PCLK, CLK_ENABLE_CLK_CPUCL1_PCLK, 3);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK, CPUCL1_DIV_CLK_CPUCL1_PCLK, CLK_ENABLE_CLK_CPUCL1_PCLK, 2);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_BUSP1_CPUCL1_IPCLKPORT_ACLK, CPUCL1_DIV_CLK_CPUCL1_PCLK, CLK_ENABLE_CLK_CPUCL1_PCLK, 1);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCM_P_CPUCL1_IPCLKPORT_I_CLK, CPUCL1_DIV_CLK_CPUCL1_PCLK, CLK_ENABLE_CLK_CPUCL1_PCLK, 0);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLKDBG, CPUCL1_DIV_CLK_CPUCL1_PCLKDBG, CLK_ENABLE_CLK_CPUCL1_PCLKDBG, 2);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_DBG_MUX_CPUCL1_IPCLKPORT_I_CLK, CPUCL1_DIV_CLK_CPUCL1_PCLKDBG, CLK_ENABLE_CLK_CPUCL1_PCLKDBG, 1);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCM_CSSYS_DBG_IPCLKPORT_PCLKM, CPUCL1_DIV_CLK_CPUCL1_PCLKDBG, CLK_ENABLE_CLK_CPUCL1_PCLKDBG, 0);
CLK_GATE(CPUCL1_GATE_CLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_I_HPM_TARGETCLK_C, CPUCL1_DIV_CLK_CPUCL1_HPM, CLK_ENABLE_CLK_CPUCL1_HPM, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK, OSCCLK, CLK_ENABLE_CLK_DISPAUD_OSCCLK, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_ENABLE_CLK_DISPAUD_BUS, 3);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_ENABLE_CLK_DISPAUD_BUS, 2);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_ENABLE_CLK_DISPAUD_BUS, 1);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_ENABLE_CLK_DISPAUD_BUS, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB, 3);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB, 2);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB, 1);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_CFW, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_ENABLE_CLK_DISPAUD_SECURE_CFW_DISP, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK, CLK_ENABLE_CLK_DISPAUD_DECON_INT_VCLK, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK, CLK_ENABLE_CLK_DISPAUD_DECON_INT_ECLK, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_TXBYTECLKHS, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS, 1);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_RXCLKESC0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0, 1);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI, DISPAUD_DIV_CLK_DISPAUD_MI2S, CLK_ENABLE_CLK_DISPAUD_MI2S, 1);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI, DISPAUD_DIV_CLK_DISPAUD_MI2S, CLK_ENABLE_CLK_DISPAUD_MI2S, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK, DISPAUD_DIV_CLK_DISPAUD_MIXER, CLK_ENABLE_CLK_DISPAUD_MIXER, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_EXT2AUD_BCK_gpio_I2S, CLKIO_DISPAUD_MIXER_SCLK_AP, CLK_ENABLE_CLKIO_DISPAUD_MIXER_SCLK_AP, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_BT_IN, CLKIO_DISPAUD_MIXER_BCLK_BT, CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_BT, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK, CLKIO_DISPAUD_MIXER_BCLK_CP, CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_CP, 0);
CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_FM_IN, CLKIO_DISPAUD_MIXER_BCLK_FM, CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_FM, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_OSCCLK, OSCCLK, CLK_ENABLE_CLK_FSYS_OSCCLK, 4);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_OSCCLK, OSCCLK, CLK_ENABLE_CLK_FSYS_OSCCLK, 3);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_OSCCLK, OSCCLK, CLK_ENABLE_CLK_FSYS_OSCCLK, 2);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK, OSCCLK, CLK_ENABLE_CLK_FSYS_OSCCLK, 1);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS, OSCCLK, CLK_ENABLE_CLK_FSYS_OSCCLK, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 24);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 23);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSP0_FSYS_IPCLKPORT_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 22);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 21);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 20);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 19);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 18);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 17);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 16);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 15);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 14);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 13);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_UPSIZER_BUS1_FSYS_IPCLKPORT_aclk, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 12);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 11);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 10);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 9);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 8);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PDMA0_IPCLKPORT_ACLK_PDMA0, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 7);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_SROMC_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 6);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 5);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BR_BUSP0_FSYS_IPCLKPORT_aclk, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 4);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 3);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 2);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 1);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_SECURE_RTIC, 1);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_SECURE_RTIC, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_SECURE_SSS, 1);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_SECURE_SSS, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PDMA1_IPCLKPORT_ACLK_PDMA1, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_SECURE_PDMA1, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_SDCLKIN, MIF_GATE_CLKCMU_FSYS_MMC0, CLK_ENABLE_CLK_FSYS_MMC0, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_SDCLKIN, MIF_GATE_CLKCMU_FSYS_MMC1, CLK_ENABLE_CLK_FSYS_MMC1, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_SDCLKIN, MIF_GATE_CLKCMU_FSYS_MMC2, CLK_ENABLE_CLK_FSYS_MMC2, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO, MIF_GATE_CLKCMU_FSYS_UFSUNIPRO, CLK_ENABLE_CLK_FSYS_UFSUNIPRO, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO_CFG, MIF_GATE_CLKCMU_FSYS_UFSUNIPRO_CFG, CLK_ENABLE_CLK_FSYS_UFSUNIPRO_CFG, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk, MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK, CLK_ENABLE_CLK_FSYS_USB20DRD_REFCLK, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK, FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, CLK_ENABLE_CLKPHY_FSYS_USB20DRD_PHYCLOCK, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_TXCLK_CH0, FSYS_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER, CLK_ENABLE_CLKPHY_FSYS_UFS_TX0_SYMBOL, 0);
CLK_GATE(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_RXCLK_CH0, FSYS_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER, CLK_ENABLE_CLKPHY_FSYS_UFS_RX0_SYMBOL, 0);
CLK_GATE(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK, OSCCLK, CLK_ENABLE_CLK_G3D_OSCCLK, 1);
CLK_GATE(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D, OSCCLK, CLK_ENABLE_CLK_G3D_OSCCLK, 0);
CLK_GATE(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 8);
CLK_GATE(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 7);
CLK_GATE(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 6);
CLK_GATE(G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 5);
CLK_GATE(G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 4);
CLK_GATE(G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 3);
CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 2);
CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 1);
CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 0);
CLK_GATE(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 6);
CLK_GATE(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 5);
CLK_GATE(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 4);
CLK_GATE(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 3);
CLK_GATE(G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 2);
CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 1);
CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 0);
CLK_GATE(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS_SECURE_CFW_G3D, 0);
CLK_GATE(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB_SECURE_CFW_G3D, 0);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK, OSCCLK, CLK_ENABLE_CLK_ISP_OSCCLK, 0);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA, ISP_MUX_CLK_ISP_VRA, CLK_ENABLE_CLK_ISP_VRA, 0);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_APB, ISP_DIV_CLK_ISP_APB, CLK_ENABLE_CLK_ISP_APB, 0);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD_PPMU, ISP_MUX_CLK_ISP_ISPD, CLK_ENABLE_CLK_ISP_ISPD, 1);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD, ISP_MUX_CLK_ISP_ISPD, CLK_ENABLE_CLK_ISP_ISPD, 0);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM, ISP_MUX_CLK_ISP_CAM, CLK_ENABLE_CLK_ISP_CAM, 0);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM_HALF, ISP_DIV_CLK_ISP_CAM_HALF, CLK_ENABLE_CLK_ISP_CAM_HALF, 0);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISP, ISP_MUX_CLK_ISP_ISP, CLK_ENABLE_CLK_ISP_ISP, 0);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4, 0);
CLK_GATE(ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4S, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4S, 0);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK, OSCCLK, CLK_ENABLE_CLK_MFCMSCL_OSCCLK, 0);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_PPMU, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_ENABLE_CLK_MFCMSCL_MSCL, 5);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_ENABLE_CLK_MFCMSCL_MSCL, 4);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_POLY, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_ENABLE_CLK_MFCMSCL_MSCL, 3);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_JPEG, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_ENABLE_CLK_MFCMSCL_MSCL, 2);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_D, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_ENABLE_CLK_MFCMSCL_MSCL, 1);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_ENABLE_CLK_MFCMSCL_MSCL, 0);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC, MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_ENABLE_CLK_MFCMSCL_MFC, 0);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB, MFCMSCL_DIV_CLK_MFCMSCL_APB, CLK_ENABLE_CLK_MFCMSCL_APB, 0);
CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_CFW, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_ENABLE_CLK_MFCMSCL_SECURE_CFW_MSCL, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_REFCLK_GEN_IPCLKPORT_I_OSC_CLK, OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 4);
CLK_GATE(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS, OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 3);
CLK_GATE(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK, OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 2);
CLK_GATE(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF, OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 1);
CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK, OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk, MIF_MUX_CLK_MIF_PHY_CLK2X, CLK_ENABLE_CLK_MIF_PHY_CLK2X, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm, MIF_DIV_CLK_MIF_PHY_CLKM, CLK_ENABLE_CLK_MIF_PHY_CLKM, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_GNSS_IPCLKPORT_ACLK_Cleany, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 27);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_ACLK_Cleany, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 26);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_CPNP, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 25);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCM_LH_GNSS_MIF_D_CP_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 24);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCM_LH_CP_MIF_D_CP_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 23);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MODEM_CPND, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 16);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MIF_CPND_MIFNP, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 15);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MIF_CPND, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 14);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_GNSS_CPND, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 13);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_CP_IPCLKPORT_ACLKS, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 4);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_RT_IPCLKPORT_ACLKS, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 3);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_NRT_IPCLKPORT_ACLKS, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 2);
CLK_GATE(MIF_GATE_CLK_MIF_UID_PPMU_GNSS_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 1);
CLK_GATE(MIF_GATE_CLK_MIF_UID_PPMU_CP_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_PERINP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 23);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNRTNP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 22);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_MIFP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 21);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MFCMSCLNP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 20);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_ISPNP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 19);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_G3DNP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 18);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_FSYSNP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 17);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_DISPAUDNP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 16);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_CPUNP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 15);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_APLNP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 14);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_PCLK_MIF_CPND_SRV, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 13);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MIF_D_RT_IPCLKPORT_PCLK_MIF_RTND_SRV, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 12);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MIF_D_NRT_IPCLKPORT_PCLK_MIF_NRTND_SRV, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 10);
CLK_GATE(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 9);
CLK_GATE(MIF_GATE_CLK_MIF_UID_PPMU_GNSS_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 8);
CLK_GATE(MIF_GATE_CLK_MIF_UID_PPMU_CP_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 7);
CLK_GATE(MIF_GATE_CLK_MIF_UID_PPMU_DMC0_RT_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 6);
CLK_GATE(MIF_GATE_CLK_MIF_UID_PPMU_DMC0_NRT_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 5);
CLK_GATE(MIF_GATE_CLK_MIF_UID_PPMU_DMC0_CPU_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 4);
CLK_GATE(MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 3);
CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 2);
CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 1);
CLK_GATE(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB0, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_GNSS_IPCLKPORT_PCLK_Mailbox, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 23);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_Mailbox, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 22);
CLK_GATE(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 21);
CLK_GATE(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 20);
CLK_GATE(MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 19);
CLK_GATE(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 18);
CLK_GATE(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 17);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 16);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKS, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 15);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKS, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 14);
CLK_GATE(MIF_GATE_CLK_MIF_UID_SFRIF_PMU_ALIVE_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 13);
CLK_GATE(MIF_GATE_CLK_MIF_UID_AHB2APB_BUS_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 12);
CLK_GATE(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 11);
CLK_GATE(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 10);
CLK_GATE(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 9);
CLK_GATE(MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 8);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_PERI_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 7);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_FSYS_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 6);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_G3D_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 5);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_MFCMSCL_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 4);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_DISPAUD_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 3);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_ISP_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 2);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_CPUCL1_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 1);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_CPUCL0_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB1, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0, 1);
CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_Mailbox_S, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB_SECURE_MODAPIF, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_CORE, MIF_DIV_CLK_MIF_CCI, CLK_ENABLE_CLK_MIF_CCI, 9);
CLK_GATE(MIF_GATE_CLK_MIF_UID_CPU1_MO_MON_IPCLKPORT_I_ACLK, MIF_DIV_CLK_MIF_CCI, CLK_ENABLE_CLK_MIF_CCI, 8);
CLK_GATE(MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK, MIF_DIV_CLK_MIF_CCI, CLK_ENABLE_CLK_MIF_CCI, 7);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_CCI, CLK_ENABLE_CLK_MIF_CCI, 6);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL1_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_CCI, CLK_ENABLE_CLK_MIF_CCI, 5);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_I_CLK, MIF_DIV_CLK_MIF_CCI, CLK_ENABLE_CLK_MIF_CCI, 4);
CLK_GATE(MIF_GATE_CLK_MIF_UID_UPSIZER_DBG_MIF_D_CCI_IPCLKPORT_aclk, MIF_DIV_CLK_MIF_CCI, CLK_ENABLE_CLK_MIF_CCI, 3);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_CPU_IPCLKPORT_ACLKS, MIF_DIV_CLK_MIF_CCI, CLK_ENABLE_CLK_MIF_CCI, 1);
CLK_GATE(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_CCI, CLK_ENABLE_CLK_MIF_CCI, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_CORE_DIV, MIF_DIV_CLK_MIF_BUSP, CLK_ENABLE_CLK_MIF_BUSP, 2);
CLK_GATE(MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK, MIF_DIV_CLK_MIF_BUSP, CLK_ENABLE_CLK_MIF_BUSP, 1);
CLK_GATE(MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK, MIF_DIV_CLK_MIF_BUSP, CLK_ENABLE_CLK_MIF_BUSP, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_INTMEM_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_BUSP, CLK_ENABLE_CLK_MIF_BUSP_SECURE_INTMEM, 0);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C, MIF_DIV_CLK_MIF_HSI2C, CLK_ENABLE_CLK_MIF_HSI2C, 6);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_1, MIF_DIV_CLK_MIF_HSI2C, CLK_ENABLE_CLK_MIF_HSI2C, 5);
CLK_GATE(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_0, MIF_DIV_CLK_MIF_HSI2C, CLK_ENABLE_CLK_MIF_HSI2C, 4);
CLK_GATE(MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iTCLK, MIF_DIV_CLK_MIF_HSI2C, CLK_ENABLE_CLK_MIF_HSI2C, 3);
CLK_GATE(MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iPCLK, MIF_DIV_CLK_MIF_HSI2C, CLK_ENABLE_CLK_MIF_HSI2C, 2);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKM, MIF_DIV_CLK_MIF_HSI2C, CLK_ENABLE_CLK_MIF_HSI2C, 1);
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKM, MIF_DIV_CLK_MIF_HSI2C, CLK_ENABLE_CLK_MIF_HSI2C, 0);
CLK_GATE(MIF_GATE_CLKCMU_CP_MEDIA_PLL, MIF_DIV_CLKCMU_CP_MEDIA_PLL, CLK_ENABLE_CLKCMU_CP_MEDIA_PLL, 0);
CLK_GATE(MIF_GATE_CLKCMU_CPUCL0_SWITCH, MIF_DIV_CLKCMU_CPUCL0_SWITCH, CLK_ENABLE_CLKCMU_CPUCL0_SWITCH, 0);
CLK_GATE(MIF_GATE_CLKCMU_CPUCL1_SWITCH, MIF_DIV_CLKCMU_CPUCL1_SWITCH, CLK_ENABLE_CLKCMU_CPUCL1_SWITCH, 0);
CLK_GATE(MIF_GATE_CLKCMU_G3D_SWITCH, MIF_DIV_CLKCMU_G3D_SWITCH, CLK_ENABLE_CLKCMU_G3D_SWITCH, 0);
CLK_GATE(MIF_GATE_CLKCMU_ISP_VRA, MIF_DIV_CLKCMU_ISP_VRA, CLK_ENABLE_CLKCMU_ISP_VRA, 0);
CLK_GATE(MIF_GATE_CLKCMU_ISP_CAM, MIF_DIV_CLKCMU_ISP_CAM, CLK_ENABLE_CLKCMU_ISP_CAM, 0);
CLK_GATE(MIF_GATE_CLKCMU_ISP_ISP, MIF_DIV_CLKCMU_ISP_ISP, CLK_ENABLE_CLKCMU_ISP_ISP, 0);
CLK_GATE(MIF_GATE_CLKCMU_DISPAUD_BUS, MIF_DIV_CLKCMU_DISPAUD_BUS, CLK_ENABLE_CLKCMU_DISPAUD_BUS, 0);
CLK_GATE(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_VCLK, 0);
CLK_GATE(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_ECLK, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK, CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_ECLK, 0);
CLK_GATE(MIF_GATE_CLKCMU_MFCMSCL_MSCL, MIF_DIV_CLKCMU_MFCMSCL_MSCL, CLK_ENABLE_CLKCMU_MFCMSCL_MSCL, 0);
CLK_GATE(MIF_GATE_CLKCMU_MFCMSCL_MFC, MIF_DIV_CLKCMU_MFCMSCL_MFC, CLK_ENABLE_CLKCMU_MFCMSCL_MFC, 0);
CLK_GATE(MIF_GATE_CLKCMU_FSYS_BUS, MIF_DIV_CLKCMU_FSYS_BUS, CLK_ENABLE_CLKCMU_FSYS_BUS, 0);
CLK_GATE(MIF_GATE_CLKCMU_FSYS_MMC0, MIF_DIV_CLKCMU_FSYS_MMC0, CLK_ENABLE_CLKCMU_FSYS_MMC0, 0);
CLK_GATE(MIF_GATE_CLKCMU_FSYS_MMC1, MIF_DIV_CLKCMU_FSYS_MMC1, CLK_ENABLE_CLKCMU_FSYS_MMC1, 0);
CLK_GATE(MIF_GATE_CLKCMU_FSYS_MMC2, MIF_DIV_CLKCMU_FSYS_MMC2, CLK_ENABLE_CLKCMU_FSYS_MMC2, 0);
CLK_GATE(MIF_GATE_CLKCMU_FSYS_UFSUNIPRO, MIF_DIV_CLKCMU_FSYS_UFSUNIPRO, CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO, 0);
CLK_GATE(MIF_GATE_CLKCMU_FSYS_UFSUNIPRO_CFG, MIF_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG, CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO_CFG, 0);
CLK_GATE(MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK, 0);
CLK_GATE(MIF_GATE_CLKCMU_PERI_BUS, MIF_DIV_CLKCMU_PERI_BUS, CLK_ENABLE_CLKCMU_PERI_BUS, 0);
CLK_GATE(MIF_GATE_CLKCMU_PERI_UART_BTWIFIFM, MIF_DIV_CLKCMU_PERI_UART_BTWIFIFM, CLK_ENABLE_CLKCMU_PERI_UART_BTWIFIFM, 0);
CLK_GATE(MIF_GATE_CLKCMU_PERI_UART_DEBUG, MIF_DIV_CLKCMU_PERI_UART_DEBUG, CLK_ENABLE_CLKCMU_PERI_UART_DEBUG, 0);
CLK_GATE(MIF_GATE_CLKCMU_PERI_UART_SENSOR, MIF_DIV_CLKCMU_PERI_UART_SENSOR, CLK_ENABLE_CLKCMU_PERI_UART_SENSOR, 0);
CLK_GATE(MIF_GATE_CLKCMU_PERI_SPI_FRONTFROM, MIF_DIV_CLKCMU_PERI_SPI_FRONTFROM, CLK_ENABLE_CLKCMU_PERI_SPI_FRONTFROM, 0);
CLK_GATE(MIF_GATE_CLKCMU_PERI_SPI_REARFROM, MIF_DIV_CLKCMU_PERI_SPI_REARFROM, CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM, 0);
CLK_GATE(MIF_GATE_CLKCMU_PERI_SPI_ESE, MIF_DIV_CLKCMU_PERI_SPI_ESE, CLK_ENABLE_CLKCMU_PERI_SPI_ESE, 0);
CLK_GATE(MIF_GATE_CLKCMU_PERI_SPI_VOICEPROCESSOR, MIF_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR, CLK_ENABLE_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0);
CLK_GATE(MIF_GATE_CLKCMU_PERI_SPI_SENSORHUB, MIF_DIV_CLKCMU_PERI_SPI_SENSORHUB, CLK_ENABLE_CLKCMU_PERI_SPI_SENSORHUB, 0);
CLK_GATE(MIF_GATE_CLKCMU_ISP_SENSOR0, MIF_DIV_CLKCMU_ISP_SENSOR0, CLK_ENABLE_CLKCMU_ISP_SENSOR0, 0);
CLK_GATE(MIF_GATE_CLKCMU_ISP_SENSOR1, MIF_DIV_CLKCMU_ISP_SENSOR1, CLK_ENABLE_CLKCMU_ISP_SENSOR1, 0);
CLK_GATE(MIF_GATE_CLKCMU_ISP_SENSOR2, MIF_DIV_CLKCMU_ISP_SENSOR2, CLK_ENABLE_CLKCMU_ISP_SENSOR2, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TMU_G3D_IPCLKPORT_I_CLK, OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 6);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TMU_CPUCL1_IPCLKPORT_I_CLK, OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 5);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK, OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 4);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK, OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 3);
CLK_GATE(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK, OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 2);
CLK_GATE(PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_OSCCLK, OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 1);
CLK_GATE(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI, OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK, OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK_SECURE_CHIPID, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 29);
CLK_GATE(PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_PCLK_S0, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 28);
CLK_GATE(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 27);
CLK_GATE(PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 26);
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 25);
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 24);
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 23);
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_TOUCHKEY_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 22);
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 21);
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_SPKAMP_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 20);
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 19);
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 18);
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_IFPMIC_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 17);
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 16);
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 15);
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_DEPTHCAM_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 14);
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 13);
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 12);
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 11);
CLK_GATE(PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 10);
CLK_GATE(PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 9);
CLK_GATE(PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 8);
CLK_GATE(PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 7);
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 6);
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 5);
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 4);
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 3);
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 2);
CLK_GATE(PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 1);
CLK_GATE(PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_WDT_CPUCL1_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 14);
CLK_GATE(PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 13);
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 12);
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 11);
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 10);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 9);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 8);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 7);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 6);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 5);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 4);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_G3D_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 3);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL1_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 2);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 1);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 10);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 9);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 8);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 7);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 6);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 5);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 4);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 3);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 2);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 1);
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_CHIPID, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_OTP_CON_TOP, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_ALIVE, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_TOP, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_EXT_UCLK, MIF_GATE_CLKCMU_PERI_UART_BTWIFIFM, CLK_ENABLE_CLK_PERI_UART_BTWIFIFM, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK, MIF_GATE_CLKCMU_PERI_UART_DEBUG, CLK_ENABLE_CLK_PERI_UART_DEBUG, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK, MIF_GATE_CLKCMU_PERI_UART_SENSOR, CLK_ENABLE_CLK_PERI_UART_SENSOR, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_SPI_EXT_CLK, MIF_GATE_CLKCMU_PERI_SPI_FRONTFROM, CLK_ENABLE_CLK_PERI_SPI_FRONTFROM, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK, MIF_GATE_CLKCMU_PERI_SPI_REARFROM, CLK_ENABLE_CLK_PERI_SPI_REARFROM, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK, MIF_GATE_CLKCMU_PERI_SPI_ESE, CLK_ENABLE_CLK_PERI_SPI_ESE, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_SPI_EXT_CLK, MIF_GATE_CLKCMU_PERI_SPI_VOICEPROCESSOR, CLK_ENABLE_CLK_PERI_SPI_VOICEPROCESSOR, 0);
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_SPI_EXT_CLK, MIF_GATE_CLKCMU_PERI_SPI_SENSORHUB, CLK_ENABLE_CLK_PERI_SPI_SENSORHUB, 0);

CLK_GATE(MIF_MUXGATE_CLKCMU_ISP_VRA,	0,	CLK_CON_MUX_CLKCMU_ISP_VRA,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_ISP_CAM,	0,	CLK_CON_MUX_CLKCMU_ISP_CAM,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_ISP_ISP,	0,	CLK_CON_MUX_CLKCMU_ISP_ISP,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_DISPAUD_BUS,	0,	CLK_CON_MUX_CLKCMU_DISPAUD_BUS,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK,	0,	CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_ECLK,	0,	CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL,	0,	CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_MFCMSCL_MFC,	0,	CLK_CON_MUX_CLKCMU_MFCMSCL_MFC,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_MMC0,	0,	CLK_CON_MUX_CLKCMU_FSYS_MMC0,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_MMC1,	0,	CLK_CON_MUX_CLKCMU_FSYS_MMC1,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_MMC2,	0,	CLK_CON_MUX_CLKCMU_FSYS_MMC2,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO,	0,	CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO_CFG,	0,	CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK,	0,	CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_UART_BTWIFIFM,	0,	CLK_CON_MUX_CLKCMU_PERI_UART_BTWIFIFM,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG,	0,	CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR,	0,	CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_SPI_FRONTFROM,	0,	CLK_CON_MUX_CLKCMU_PERI_SPI_FRONTFROM,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM,	0,	CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_SPI_ESE,	0,	CLK_CON_MUX_CLKCMU_PERI_SPI_ESE,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_SPI_VOICEPROCESSOR,	0,	CLK_CON_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_SPI_SENSORHUB,	0,	CLK_CON_MUX_CLKCMU_PERI_SPI_SENSORHUB,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_ISP_SENSOR0,	0,	CLK_CON_MUX_CLKCMU_ISP_SENSOR0,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_ISP_SENSOR1,	0,	CLK_CON_MUX_CLKCMU_ISP_SENSOR1,	21);
CLK_GATE(MIF_MUXGATE_CLKCMU_ISP_SENSOR2,	0,	CLK_CON_MUX_CLKCMU_ISP_SENSOR2,	21);

CLK_GATE(PMU_DEBUG_CLKOUT_SEL08,	OSCCLK,	PMU_PMU_DEBUG,	8);
CLK_GATE(PMU_DEBUG_CLKOUT_SEL09,	OSCCLK,	PMU_PMU_DEBUG,	9);
CLK_GATE(PMU_DEBUG_CLKOUT_SEL10,	OSCCLK,	PMU_PMU_DEBUG,	10);
CLK_GATE(PMU_DEBUG_CLKOUT_SEL11,	OSCCLK,	PMU_PMU_DEBUG,	11);
CLK_GATE(PMU_DEBUG_CLKOUT_SEL12,	OSCCLK,	PMU_PMU_DEBUG,	12);
CLK_GATE(PMU_DEBUG_CLKOUT_DISABLE,	OSCCLK,	PMU_PMU_DEBUG,	0);


int _pwrcal_is_private_mux_set_src(struct pwrcal_clk *clk)
{
	return 0;
}

int _pwrcal_private_mux_set_src(struct pwrcal_clk *clk, unsigned int src)
{
	return 0;
}

static int strcmp_unalign_address(const char *src1, const char *src2)
{
	for (; *src1 == *src2; src1++, src2++)
		if (*src1 == '\0')
			return 0;

	return ((*(unsigned char *)src1 < *(unsigned char *)src2) ? -1 : 1);
}

static struct pwrcal_clk *clk_get_with_list(char *clk_name, struct pwrcal_clk **clk_list, int clk_count)
{
	int i;

	for (i = 0; i < clk_count; ++i) {
		if (strcmp_unalign_address(clk_list[i]->name, clk_name) == 0)
			return clk_list[i];
	}

	return NULL;
}

struct pwrcal_clk *clk_find(char *clk_name)
{
	struct pwrcal_clk *ret_cal = NULL;

	if (strstr(clk_name, "PLL"))
		ret_cal = clk_get_with_list(clk_name, pll_type_list, NUM_OF_PLL_TYPE);

	if (strstr(clk_name, "DIV"))
		ret_cal = clk_get_with_list(clk_name, div_type_list, NUM_OF_DIV_TYPE);

	if (strstr(clk_name, "MUX"))
		ret_cal = clk_get_with_list(clk_name, mux_type_list, NUM_OF_MUX_TYPE);

	if (strstr(clk_name, "GATE"))
		ret_cal = clk_get_with_list(clk_name, gate_type_list, NUM_OF_GATE_TYPE);

	return ret_cal;
}

void clk_pll_set_rate_table(struct pwrcal_pll *pll)
{
	int i;
	void *pll_block;
	struct pwrcal_pll_rate_table *pll_rate_table;
	struct ect_pll *pll_unit;
	struct ect_pll_frequency *pll_frequency;

	if (pll == NULL)
		return;

	pll_block = ect_get_block(BLOCK_PLL);
	if (pll_block == NULL)
		return;

	pll_unit = ect_pll_get_pll(pll_block, (char *)pll->clk.name);
	if (pll_unit == NULL)
		return;

	pll_rate_table = kzalloc(sizeof(struct pwrcal_pll_rate_table) * pll_unit->num_of_frequency, GFP_KERNEL);
	if (pll_rate_table == NULL)
		return;

	for (i = 0; i < pll_unit->num_of_frequency; ++i) {
		pll_frequency = &pll_unit->frequency_list[i];

		pll_rate_table[i].rate = pll_frequency->frequency;
		pll_rate_table[i].pdiv = pll_frequency->p;
		pll_rate_table[i].mdiv = pll_frequency->m;
		pll_rate_table[i].sdiv = pll_frequency->s;
		pll_rate_table[i].kdiv = pll_frequency->k;
	}

	pll->rate_table = pll_rate_table;
	pll->rate_count = pll_unit->num_of_frequency;
}

void clk_init(void)
{
	ADD_CLK_TO_LIST(pll_type_list, CPUCL0_PLL);
	ADD_CLK_TO_LIST(pll_type_list, CPUCL1_PLL);
	ADD_CLK_TO_LIST(pll_type_list, MEM_PLL);
	ADD_CLK_TO_LIST(pll_type_list, BUS_PLL);
	ADD_CLK_TO_LIST(pll_type_list, MEDIA_PLL);
	ADD_CLK_TO_LIST(pll_type_list, G3D_PLL);
	ADD_CLK_TO_LIST(pll_type_list, USB_PLL);
	ADD_CLK_TO_LIST(pll_type_list, ISP_PLL);
	ADD_CLK_TO_LIST(pll_type_list, DISP_PLL);
	ADD_CLK_TO_LIST(pll_type_list, AUD_PLL);

	ADD_CLK_TO_LIST(fixed_rate_type_list, OSCCLK);
	ADD_CLK_TO_LIST(fixed_rate_type_list, OSCCLK_26M);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_FSYS_USB20DRD_PHYCLOCK);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_FSYS_UFS_TX0_SYMBOL);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_FSYS_UFS_RX0_SYMBOL);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKIO_DISPAUD_AUDIOCDCLK0);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKIO_DISPAUD_MIXER_SCLK_AP);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKIO_DISPAUD_MIXER_BCLK_BT);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKIO_DISPAUD_MIXER_BCLK_CP);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKIO_DISPAUD_MIXER_BCLK_FM);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_ISP_S_RXBYTECLKHS0_S4);
	ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_ISP_S_RXBYTECLKHS0_S4S);
	ADD_CLK_TO_LIST(fixed_rate_type_list, FIN_TEMP);

	ADD_CLK_TO_LIST(fixed_factor_type_list, MIF_FF_MUX_MEM_PLL_DIV2);
	ADD_CLK_TO_LIST(fixed_factor_type_list, MIF_FF_MUX_MEDIA_PLL_DIV2);
	ADD_CLK_TO_LIST(fixed_factor_type_list, MIF_FF_MUX_BUS_PLL_DIV2);

	ADD_CLK_TO_LIST(mux_type_list, CPUCL0_MUX_CPUCL0_PLL);
	ADD_CLK_TO_LIST(mux_type_list, CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER);
	ADD_CLK_TO_LIST(mux_type_list, CPUCL0_MUX_CLK_CPUCL0);
	ADD_CLK_TO_LIST(mux_type_list, CPUCL1_MUX_CPUCL1_PLL);
	ADD_CLK_TO_LIST(mux_type_list, CPUCL1_MUX_CLKCMU_CPUCL1_SWITCH_USER);
	ADD_CLK_TO_LIST(mux_type_list, CPUCL1_MUX_CLK_CPUCL1);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_DISP_PLL);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_AUD_PLL);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLK_DISPAUD_DECON_INT_VCLK);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLK_DISPAUD_DECON_INT_ECLK);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER);
	ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLK_DISPAUD_MI2S);
	ADD_CLK_TO_LIST(mux_type_list, FSYS_MUX_USB_PLL);
	ADD_CLK_TO_LIST(mux_type_list, FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER);
	ADD_CLK_TO_LIST(mux_type_list, FSYS_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER);
	ADD_CLK_TO_LIST(mux_type_list, FSYS_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER);
	ADD_CLK_TO_LIST(mux_type_list, G3D_MUX_G3D_PLL);
	ADD_CLK_TO_LIST(mux_type_list, G3D_MUX_CLKCMU_G3D_SWITCH_USER);
	ADD_CLK_TO_LIST(mux_type_list, G3D_MUX_CLK_G3D);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_ISP_PLL);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLKCMU_ISP_VRA_USER);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLKCMU_ISP_CAM_USER);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLKCMU_ISP_ISP_USER);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLK_ISP_VRA);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLK_ISP_CAM);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLK_ISP_ISP);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLK_ISP_ISPD);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER);
	ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER);
	ADD_CLK_TO_LIST(mux_type_list, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER);
	ADD_CLK_TO_LIST(mux_type_list, MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_MEM_PLL);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_MEDIA_PLL);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_BUS_PLL);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLK_MIF_PHY_CLK2X);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLK_MIF_PHY_SWITCH);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLK_MIF_BUSD);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLK_MIF_CCI);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_ISP_VRA);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_ISP_CAM);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_ISP_ISP);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_DISPAUD_BUS);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_MFCMSCL_MSCL);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_MFCMSCL_MFC);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_BUS);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_MMC0);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_MMC1);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_MMC2);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_UFSUNIPRO);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_BUS);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_UART_BTWIFIFM);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_UART_DEBUG);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_UART_SENSOR);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_SPI_FRONTFROM);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_SPI_REARFROM);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_SPI_ESE);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_SPI_SENSORHUB);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_ISP_SENSOR0);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_ISP_SENSOR1);
	ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_ISP_SENSOR2);

	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_1);
	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_2);
	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_ACLK);
	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_PCLK);
	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_ATCLK);
	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG);
	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_CNTCLK);
	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR);
	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_HPM);
	ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_PLL);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_1);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_2);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_ACLK);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_PCLK);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_ATCLK);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_PCLKDBG);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_CNTCLK);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_RUN_MONITOR);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_HPM);
	ADD_CLK_TO_LIST(div_type_list, CPUCL1_DIV_CLK_CPUCL1_PLL);
	ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_APB);
	ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK);
	ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK);
	ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_MI2S);
	ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_MIXER);
	ADD_CLK_TO_LIST(div_type_list, G3D_DIV_CLK_G3D_BUS);
	ADD_CLK_TO_LIST(div_type_list, G3D_DIV_CLK_G3D_APB);
	ADD_CLK_TO_LIST(div_type_list, ISP_DIV_CLK_ISP_APB);
	ADD_CLK_TO_LIST(div_type_list, ISP_DIV_CLK_ISP_CAM_HALF);
	ADD_CLK_TO_LIST(div_type_list, MFCMSCL_DIV_CLK_MFCMSCL_APB);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_PHY_CLKM);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_BUSD);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_APB);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_CCI);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_BUSP);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_HSI2C);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_CP_MEDIA_PLL);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_CPUCL0_SWITCH);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_CPUCL1_SWITCH);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_G3D_SWITCH);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_ISP_VRA);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_ISP_CAM);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_ISP_ISP);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_DISPAUD_BUS);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_MFCMSCL_MSCL);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_MFCMSCL_MFC);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_BUS);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_MMC0);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_MMC1);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_MMC2);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_UFSUNIPRO);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_BUS);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_UART_BTWIFIFM);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_UART_DEBUG);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_UART_SENSOR);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_SPI_FRONTFROM);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_SPI_REARFROM);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_SPI_ESE);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_SPI_SENSORHUB);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_ISP_SENSOR0);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_ISP_SENSOR1);
	ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_ISP_SENSOR2);

	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_I_CLK__PMU_CPUCL1);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCS_D_CPUCL1_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_I_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_BUSP1_CPUCL1_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCM_P_CPUCL1_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLKDBG);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_DBG_MUX_CPUCL1_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCM_CSSYS_DBG_IPCLKPORT_PCLKM);
	ADD_CLK_TO_LIST(gate_type_list, CPUCL1_GATE_CLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_I_HPM_TARGETCLK_C);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_CFW);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_TXBYTECLKHS);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_RXCLKESC0);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_EXT2AUD_BCK_gpio_I2S);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_BT_IN);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK);
	ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_FM_IN);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_OSCCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_OSCCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_OSCCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSP0_FSYS_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_UPSIZER_BUS1_FSYS_IPCLKPORT_aclk);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PDMA0_IPCLKPORT_ACLK_PDMA0);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_SROMC_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BR_BUSP0_FSYS_IPCLKPORT_aclk);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PDMA1_IPCLKPORT_ACLK_PDMA1);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_SDCLKIN);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_SDCLKIN);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_SDCLKIN);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO_CFG);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_TXCLK_CH0);
	ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_RXCLK_CH0);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_APB);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD_PPMU);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM_HALF);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_ISP);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4);
	ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4S);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_PPMU);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_POLY);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_JPEG);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_D);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB);
	ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_CFW);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_REFCLK_GEN_IPCLKPORT_I_OSC_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_GNSS_IPCLKPORT_ACLK_Cleany);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_ACLK_Cleany);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_CPNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCM_LH_GNSS_MIF_D_CP_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCM_LH_CP_MIF_D_CP_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MODEM_CPND);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MIF_CPND_MIFNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MIF_CPND);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_GNSS_CPND);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_CP_IPCLKPORT_ACLKS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_RT_IPCLKPORT_ACLKS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_NRT_IPCLKPORT_ACLKS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PPMU_GNSS_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PPMU_CP_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_PERINP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNRTNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_MIFP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MFCMSCLNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_ISPNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_G3DNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_FSYSNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_DISPAUDNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_CPUNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_APLNP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_PCLK_MIF_CPND_SRV);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MIF_D_RT_IPCLKPORT_PCLK_MIF_RTND_SRV);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MIF_D_NRT_IPCLKPORT_PCLK_MIF_NRTND_SRV);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PPMU_GNSS_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PPMU_CP_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PPMU_DMC0_RT_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PPMU_DMC0_NRT_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PPMU_DMC0_CPU_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_GNSS_IPCLKPORT_PCLK_Mailbox);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_Mailbox);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SFRIF_PMU_ALIVE_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AHB2APB_BUS_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_PERI_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_FSYS_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_G3D_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_MFCMSCL_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_DISPAUD_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_ISP_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_CPUCL1_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_CPUCL0_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_Mailbox_S);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_CORE);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_CPU1_MO_MON_IPCLKPORT_I_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL1_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_UPSIZER_DBG_MIF_D_CCI_IPCLKPORT_aclk);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_CPU_IPCLKPORT_ACLKS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_CORE_DIV);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_INTMEM_IPCLKPORT_ACLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_1);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_0);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iTCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iPCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_CP_MEDIA_PLL);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_CPUCL0_SWITCH);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_CPUCL1_SWITCH);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_G3D_SWITCH);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_ISP_VRA);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_ISP_CAM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_ISP_ISP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_DISPAUD_BUS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_DISPAUD_DECON_INT_ECLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_MFCMSCL_MSCL);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_MFCMSCL_MFC);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_BUS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_MMC0);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_MMC1);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_MMC2);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_UFSUNIPRO);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_UFSUNIPRO_CFG);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_BUS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_UART_BTWIFIFM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_UART_DEBUG);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_UART_SENSOR);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_SPI_FRONTFROM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_SPI_REARFROM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_SPI_ESE);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_SPI_VOICEPROCESSOR);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_SPI_SENSORHUB);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_ISP_SENSOR0);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_ISP_SENSOR1);
	ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_ISP_SENSOR2);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TMU_G3D_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TMU_CPUCL1_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_OSCCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_PCLK_S0);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_TOUCHKEY_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_SPKAMP_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_IFPMIC_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_DEPTHCAM_IPCLKPORT_iPCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_WDT_CPUCL1_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_TMU_G3D_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL1_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_EXT_UCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_SPI_EXT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_SPI_EXT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_SPI_EXT_CLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_ISP_VRA);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_ISP_CAM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_ISP_ISP);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_DISPAUD_BUS);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_ECLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_MFCMSCL_MFC);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_MMC0);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_MMC1);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_MMC2);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO_CFG);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_UART_BTWIFIFM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_SPI_FRONTFROM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_SPI_ESE);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_SPI_VOICEPROCESSOR);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_SPI_SENSORHUB);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_ISP_SENSOR0);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_ISP_SENSOR1);
	ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_ISP_SENSOR2);

	ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL08);
	ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL09);
	ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL10);
	ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL11);
	ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL12);
	ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_DISABLE);

	clk_pll_set_rate_table(&clk_CPUCL0_PLL);
	clk_pll_set_rate_table(&clk_CPUCL1_PLL);
	clk_pll_set_rate_table(&clk_MEM_PLL);
	clk_pll_set_rate_table(&clk_BUS_PLL);
	clk_pll_set_rate_table(&clk_MEDIA_PLL);
	clk_pll_set_rate_table(&clk_G3D_PLL);
	clk_pll_set_rate_table(&clk_USB_PLL);
	clk_pll_set_rate_table(&clk_ISP_PLL);
	clk_pll_set_rate_table(&clk_DISP_PLL);
	clk_pll_set_rate_table(&clk_AUD_PLL);

	/*gating non used clocks*/
	pwrcal_gate_disable(CLK(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_ACLK));
	pwrcal_gate_disable(CLK(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO));
	pwrcal_gate_disable(CLK(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO_CFG));
	pwrcal_gate_disable(CLK(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_TXCLK_CH0));
	pwrcal_gate_disable(CLK(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_RXCLK_CH0));
	pwrcal_gate_disable(CLK(PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_PCLK_S0));
	pwrcal_gate_disable(CLK(PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_OSCCLK));
}