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ciss.c
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ciss.c
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/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2001 Michael Smith
* Copyright (c) 2004 Paul Saab
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* Common Interface for SCSI-3 Support driver.
*
* CISS claims to provide a common interface between a generic SCSI
* transport and an intelligent host adapter.
*
* This driver supports CISS as defined in the document "CISS Command
* Interface for SCSI-3 Support Open Specification", Version 1.04,
* Valence Number 1, dated 20001127, produced by Compaq Computer
* Corporation. This document appears to be a hastily and somewhat
* arbitrarlily cut-down version of a larger (and probably even more
* chaotic and inconsistent) Compaq internal document. Various
* details were also gleaned from Compaq's "cciss" driver for Linux.
*
* We provide a shim layer between the CISS interface and CAM,
* offloading most of the queueing and being-a-disk chores onto CAM.
* Entry to the driver is via the PCI bus attachment (ciss_probe,
* ciss_attach, etc) and via the CAM interface (ciss_cam_action,
* ciss_cam_poll). The Compaq CISS adapters are, however, poor SCSI
* citizens and we have to fake up some responses to get reasonable
* behaviour out of them. In addition, the CISS command set is by no
* means adequate to support the functionality of a RAID controller,
* and thus the supported Compaq adapters utilise portions of the
* control protocol from earlier Compaq adapter families.
*
* Note that we only support the "simple" transport layer over PCI.
* This interface (ab)uses the I2O register set (specifically the post
* queues) to exchange commands with the adapter. Other interfaces
* are available, but we aren't supposed to know about them, and it is
* dubious whether they would provide major performance improvements
* except under extreme load.
*
* Currently the only supported CISS adapters are the Compaq Smart
* Array 5* series (5300, 5i, 532). Even with only three adapters,
* Compaq still manage to have interface variations.
*
*
* Thanks must go to Fred Harris and Darryl DeVinney at Compaq, as
* well as Paul Saab at Yahoo! for their assistance in making this
* driver happen.
*
* More thanks must go to John Cagle at HP for the countless hours
* spent making this driver "work" with the MSA* series storage
* enclosures. Without his help (and nagging), this driver could not
* be used with these enclosures.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/stat.h>
#include <sys/kthread.h>
#include <sys/queue.h>
#include <sys/sysctl.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/cam_periph.h>
#include <cam/cam_sim.h>
#include <cam/cam_xpt_sim.h>
#include <cam/scsi/scsi_all.h>
#include <cam/scsi/scsi_message.h>
#include <machine/bus.h>
#include <machine/endian.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/ciss/cissreg.h>
#include <dev/ciss/cissio.h>
#include <dev/ciss/cissvar.h>
static MALLOC_DEFINE(CISS_MALLOC_CLASS, "ciss_data",
"ciss internal data buffers");
/* pci interface */
static int ciss_lookup(device_t dev);
static int ciss_probe(device_t dev);
static int ciss_attach(device_t dev);
static int ciss_detach(device_t dev);
static int ciss_shutdown(device_t dev);
/* (de)initialisation functions, control wrappers */
static int ciss_init_pci(struct ciss_softc *sc);
static int ciss_setup_msix(struct ciss_softc *sc);
static int ciss_init_perf(struct ciss_softc *sc);
static int ciss_wait_adapter(struct ciss_softc *sc);
static int ciss_flush_adapter(struct ciss_softc *sc);
static int ciss_init_requests(struct ciss_softc *sc);
static void ciss_command_map_helper(void *arg, bus_dma_segment_t *segs,
int nseg, int error);
static int ciss_identify_adapter(struct ciss_softc *sc);
static int ciss_init_logical(struct ciss_softc *sc);
static int ciss_init_physical(struct ciss_softc *sc);
static int ciss_filter_physical(struct ciss_softc *sc, struct ciss_lun_report *cll);
static int ciss_identify_logical(struct ciss_softc *sc, struct ciss_ldrive *ld);
static int ciss_get_ldrive_status(struct ciss_softc *sc, struct ciss_ldrive *ld);
static int ciss_update_config(struct ciss_softc *sc);
static int ciss_accept_media(struct ciss_softc *sc, struct ciss_ldrive *ld);
static void ciss_init_sysctl(struct ciss_softc *sc);
static void ciss_soft_reset(struct ciss_softc *sc);
static void ciss_free(struct ciss_softc *sc);
static void ciss_spawn_notify_thread(struct ciss_softc *sc);
static void ciss_kill_notify_thread(struct ciss_softc *sc);
/* request submission/completion */
static int ciss_start(struct ciss_request *cr);
static void ciss_done(struct ciss_softc *sc, cr_qhead_t *qh);
static void ciss_perf_done(struct ciss_softc *sc, cr_qhead_t *qh);
static void ciss_intr(void *arg);
static void ciss_perf_intr(void *arg);
static void ciss_perf_msi_intr(void *arg);
static void ciss_complete(struct ciss_softc *sc, cr_qhead_t *qh);
static int _ciss_report_request(struct ciss_request *cr, int *command_status, int *scsi_status, const char *func);
static int ciss_synch_request(struct ciss_request *cr, int timeout);
static int ciss_poll_request(struct ciss_request *cr, int timeout);
static int ciss_wait_request(struct ciss_request *cr, int timeout);
#if 0
static int ciss_abort_request(struct ciss_request *cr);
#endif
/* request queueing */
static int ciss_get_request(struct ciss_softc *sc, struct ciss_request **crp);
static void ciss_preen_command(struct ciss_request *cr);
static void ciss_release_request(struct ciss_request *cr);
/* request helpers */
static int ciss_get_bmic_request(struct ciss_softc *sc, struct ciss_request **crp,
int opcode, void **bufp, size_t bufsize);
static int ciss_user_command(struct ciss_softc *sc, IOCTL_Command_struct *ioc);
/* DMA map/unmap */
static int ciss_map_request(struct ciss_request *cr);
static void ciss_request_map_helper(void *arg, bus_dma_segment_t *segs,
int nseg, int error);
static void ciss_unmap_request(struct ciss_request *cr);
/* CAM interface */
static int ciss_cam_init(struct ciss_softc *sc);
static void ciss_cam_rescan_target(struct ciss_softc *sc,
int bus, int target);
static void ciss_cam_action(struct cam_sim *sim, union ccb *ccb);
static int ciss_cam_action_io(struct cam_sim *sim, struct ccb_scsiio *csio);
static int ciss_cam_emulate(struct ciss_softc *sc, struct ccb_scsiio *csio);
static void ciss_cam_poll(struct cam_sim *sim);
static void ciss_cam_complete(struct ciss_request *cr);
static void ciss_cam_complete_fixup(struct ciss_softc *sc, struct ccb_scsiio *csio);
static int ciss_name_device(struct ciss_softc *sc, int bus, int target);
/* periodic status monitoring */
static void ciss_periodic(void *arg);
static void ciss_nop_complete(struct ciss_request *cr);
static void ciss_disable_adapter(struct ciss_softc *sc);
static void ciss_notify_event(struct ciss_softc *sc);
static void ciss_notify_complete(struct ciss_request *cr);
static int ciss_notify_abort(struct ciss_softc *sc);
static int ciss_notify_abort_bmic(struct ciss_softc *sc);
static void ciss_notify_hotplug(struct ciss_softc *sc, struct ciss_notify *cn);
static void ciss_notify_logical(struct ciss_softc *sc, struct ciss_notify *cn);
static void ciss_notify_physical(struct ciss_softc *sc, struct ciss_notify *cn);
/* debugging output */
static void ciss_print_request(struct ciss_request *cr);
static void ciss_print_ldrive(struct ciss_softc *sc, struct ciss_ldrive *ld);
static const char *ciss_name_ldrive_status(int status);
static int ciss_decode_ldrive_status(int status);
static const char *ciss_name_ldrive_org(int org);
static const char *ciss_name_command_status(int status);
/*
* PCI bus interface.
*/
static device_method_t ciss_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, ciss_probe),
DEVMETHOD(device_attach, ciss_attach),
DEVMETHOD(device_detach, ciss_detach),
DEVMETHOD(device_shutdown, ciss_shutdown),
{ 0, 0 }
};
static driver_t ciss_pci_driver = {
"ciss",
ciss_methods,
sizeof(struct ciss_softc)
};
/*
* Control device interface.
*/
static d_open_t ciss_open;
static d_close_t ciss_close;
static d_ioctl_t ciss_ioctl;
static struct cdevsw ciss_cdevsw = {
.d_version = D_VERSION,
.d_flags = 0,
.d_open = ciss_open,
.d_close = ciss_close,
.d_ioctl = ciss_ioctl,
.d_name = "ciss",
};
/*
* This tunable can be set at boot time and controls whether physical devices
* that are marked hidden by the firmware should be exposed anyways.
*/
static unsigned int ciss_expose_hidden_physical = 0;
TUNABLE_INT("hw.ciss.expose_hidden_physical", &ciss_expose_hidden_physical);
static unsigned int ciss_nop_message_heartbeat = 0;
TUNABLE_INT("hw.ciss.nop_message_heartbeat", &ciss_nop_message_heartbeat);
/*
* This tunable can force a particular transport to be used:
* <= 0 : use default
* 1 : force simple
* 2 : force performant
*/
static int ciss_force_transport = 0;
TUNABLE_INT("hw.ciss.force_transport", &ciss_force_transport);
/*
* This tunable can force a particular interrupt delivery method to be used:
* <= 0 : use default
* 1 : force INTx
* 2 : force MSIX
*/
static int ciss_force_interrupt = 0;
TUNABLE_INT("hw.ciss.force_interrupt", &ciss_force_interrupt);
/************************************************************************
* CISS adapters amazingly don't have a defined programming interface
* value. (One could say some very despairing things about PCI and
* people just not getting the general idea.) So we are forced to
* stick with matching against subvendor/subdevice, and thus have to
* be updated for every new CISS adapter that appears.
*/
#define CISS_BOARD_UNKNWON 0
#define CISS_BOARD_SA5 1
#define CISS_BOARD_SA5B 2
#define CISS_BOARD_NOMSI (1<<4)
#define CISS_BOARD_SIMPLE (1<<5)
static struct
{
u_int16_t subvendor;
u_int16_t subdevice;
int flags;
char *desc;
} ciss_vendor_data[] = {
{ 0x0e11, 0x4070, CISS_BOARD_SA5|CISS_BOARD_NOMSI|CISS_BOARD_SIMPLE,
"Compaq Smart Array 5300" },
{ 0x0e11, 0x4080, CISS_BOARD_SA5B|CISS_BOARD_NOMSI, "Compaq Smart Array 5i" },
{ 0x0e11, 0x4082, CISS_BOARD_SA5B|CISS_BOARD_NOMSI, "Compaq Smart Array 532" },
{ 0x0e11, 0x4083, CISS_BOARD_SA5B|CISS_BOARD_NOMSI, "HP Smart Array 5312" },
{ 0x0e11, 0x4091, CISS_BOARD_SA5, "HP Smart Array 6i" },
{ 0x0e11, 0x409A, CISS_BOARD_SA5, "HP Smart Array 641" },
{ 0x0e11, 0x409B, CISS_BOARD_SA5, "HP Smart Array 642" },
{ 0x0e11, 0x409C, CISS_BOARD_SA5, "HP Smart Array 6400" },
{ 0x0e11, 0x409D, CISS_BOARD_SA5, "HP Smart Array 6400 EM" },
{ 0x103C, 0x3211, CISS_BOARD_SA5, "HP Smart Array E200i" },
{ 0x103C, 0x3212, CISS_BOARD_SA5, "HP Smart Array E200" },
{ 0x103C, 0x3213, CISS_BOARD_SA5, "HP Smart Array E200i" },
{ 0x103C, 0x3214, CISS_BOARD_SA5, "HP Smart Array E200i" },
{ 0x103C, 0x3215, CISS_BOARD_SA5, "HP Smart Array E200i" },
{ 0x103C, 0x3220, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x3222, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x3223, CISS_BOARD_SA5, "HP Smart Array P800" },
{ 0x103C, 0x3225, CISS_BOARD_SA5, "HP Smart Array P600" },
{ 0x103C, 0x3230, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x3231, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x3232, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x3233, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x3234, CISS_BOARD_SA5, "HP Smart Array P400" },
{ 0x103C, 0x3235, CISS_BOARD_SA5, "HP Smart Array P400i" },
{ 0x103C, 0x3236, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x3237, CISS_BOARD_SA5, "HP Smart Array E500" },
{ 0x103C, 0x3238, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x3239, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x323A, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x323B, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x323C, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x323D, CISS_BOARD_SA5, "HP Smart Array P700m" },
{ 0x103C, 0x3241, CISS_BOARD_SA5, "HP Smart Array P212" },
{ 0x103C, 0x3243, CISS_BOARD_SA5, "HP Smart Array P410" },
{ 0x103C, 0x3245, CISS_BOARD_SA5, "HP Smart Array P410i" },
{ 0x103C, 0x3247, CISS_BOARD_SA5, "HP Smart Array P411" },
{ 0x103C, 0x3249, CISS_BOARD_SA5, "HP Smart Array P812" },
{ 0x103C, 0x324A, CISS_BOARD_SA5, "HP Smart Array P712m" },
{ 0x103C, 0x324B, CISS_BOARD_SA5, "HP Smart Array" },
{ 0x103C, 0x3350, CISS_BOARD_SA5, "HP Smart Array P222" },
{ 0x103C, 0x3351, CISS_BOARD_SA5, "HP Smart Array P420" },
{ 0x103C, 0x3352, CISS_BOARD_SA5, "HP Smart Array P421" },
{ 0x103C, 0x3353, CISS_BOARD_SA5, "HP Smart Array P822" },
{ 0x103C, 0x3354, CISS_BOARD_SA5, "HP Smart Array P420i" },
{ 0x103C, 0x3355, CISS_BOARD_SA5, "HP Smart Array P220i" },
{ 0x103C, 0x3356, CISS_BOARD_SA5, "HP Smart Array P721m" },
{ 0x103C, 0x1920, CISS_BOARD_SA5, "HP Smart Array P430i" },
{ 0x103C, 0x1921, CISS_BOARD_SA5, "HP Smart Array P830i" },
{ 0x103C, 0x1922, CISS_BOARD_SA5, "HP Smart Array P430" },
{ 0x103C, 0x1923, CISS_BOARD_SA5, "HP Smart Array P431" },
{ 0x103C, 0x1924, CISS_BOARD_SA5, "HP Smart Array P830" },
{ 0x103C, 0x1926, CISS_BOARD_SA5, "HP Smart Array P731m" },
{ 0x103C, 0x1928, CISS_BOARD_SA5, "HP Smart Array P230i" },
{ 0x103C, 0x1929, CISS_BOARD_SA5, "HP Smart Array P530" },
{ 0x103C, 0x192A, CISS_BOARD_SA5, "HP Smart Array P531" },
{ 0x103C, 0x21BD, CISS_BOARD_SA5, "HP Smart Array P244br" },
{ 0x103C, 0x21BE, CISS_BOARD_SA5, "HP Smart Array P741m" },
{ 0x103C, 0x21BF, CISS_BOARD_SA5, "HP Smart Array H240ar" },
{ 0x103C, 0x21C0, CISS_BOARD_SA5, "HP Smart Array P440ar" },
{ 0x103C, 0x21C1, CISS_BOARD_SA5, "HP Smart Array P840ar" },
{ 0x103C, 0x21C2, CISS_BOARD_SA5, "HP Smart Array P440" },
{ 0x103C, 0x21C3, CISS_BOARD_SA5, "HP Smart Array P441" },
{ 0x103C, 0x21C5, CISS_BOARD_SA5, "HP Smart Array P841" },
{ 0x103C, 0x21C6, CISS_BOARD_SA5, "HP Smart Array H244br" },
{ 0x103C, 0x21C7, CISS_BOARD_SA5, "HP Smart Array H240" },
{ 0x103C, 0x21C8, CISS_BOARD_SA5, "HP Smart Array H241" },
{ 0x103C, 0x21CA, CISS_BOARD_SA5, "HP Smart Array P246br" },
{ 0x103C, 0x21CB, CISS_BOARD_SA5, "HP Smart Array P840" },
{ 0x103C, 0x21CC, CISS_BOARD_SA5, "HP Smart Array P542d" },
{ 0x103C, 0x21CD, CISS_BOARD_SA5, "HP Smart Array P240nr" },
{ 0x103C, 0x21CE, CISS_BOARD_SA5, "HP Smart Array H240nr" },
{ 0, 0, 0, NULL }
};
static devclass_t ciss_devclass;
DRIVER_MODULE(ciss, pci, ciss_pci_driver, ciss_devclass, 0, 0);
MODULE_PNP_INFO("U16:vendor;U16:device;", pci, ciss, ciss_vendor_data,
nitems(ciss_vendor_data) - 1);
MODULE_DEPEND(ciss, cam, 1, 1, 1);
MODULE_DEPEND(ciss, pci, 1, 1, 1);
/************************************************************************
* Find a match for the device in our list of known adapters.
*/
static int
ciss_lookup(device_t dev)
{
int i;
for (i = 0; ciss_vendor_data[i].desc != NULL; i++)
if ((pci_get_subvendor(dev) == ciss_vendor_data[i].subvendor) &&
(pci_get_subdevice(dev) == ciss_vendor_data[i].subdevice)) {
return(i);
}
return(-1);
}
/************************************************************************
* Match a known CISS adapter.
*/
static int
ciss_probe(device_t dev)
{
int i;
i = ciss_lookup(dev);
if (i != -1) {
device_set_desc(dev, ciss_vendor_data[i].desc);
return(BUS_PROBE_DEFAULT);
}
return(ENOENT);
}
/************************************************************************
* Attach the driver to this adapter.
*/
static int
ciss_attach(device_t dev)
{
struct ciss_softc *sc;
int error;
debug_called(1);
#ifdef CISS_DEBUG
/* print structure/union sizes */
debug_struct(ciss_command);
debug_struct(ciss_header);
debug_union(ciss_device_address);
debug_struct(ciss_cdb);
debug_struct(ciss_report_cdb);
debug_struct(ciss_notify_cdb);
debug_struct(ciss_notify);
debug_struct(ciss_message_cdb);
debug_struct(ciss_error_info_pointer);
debug_struct(ciss_error_info);
debug_struct(ciss_sg_entry);
debug_struct(ciss_config_table);
debug_struct(ciss_bmic_cdb);
debug_struct(ciss_bmic_id_ldrive);
debug_struct(ciss_bmic_id_lstatus);
debug_struct(ciss_bmic_id_table);
debug_struct(ciss_bmic_id_pdrive);
debug_struct(ciss_bmic_blink_pdrive);
debug_struct(ciss_bmic_flush_cache);
debug_const(CISS_MAX_REQUESTS);
debug_const(CISS_MAX_LOGICAL);
debug_const(CISS_INTERRUPT_COALESCE_DELAY);
debug_const(CISS_INTERRUPT_COALESCE_COUNT);
debug_const(CISS_COMMAND_ALLOC_SIZE);
debug_const(CISS_COMMAND_SG_LENGTH);
debug_type(cciss_pci_info_struct);
debug_type(cciss_coalint_struct);
debug_type(cciss_coalint_struct);
debug_type(NodeName_type);
debug_type(NodeName_type);
debug_type(Heartbeat_type);
debug_type(BusTypes_type);
debug_type(FirmwareVer_type);
debug_type(DriverVer_type);
debug_type(IOCTL_Command_struct);
#endif
sc = device_get_softc(dev);
sc->ciss_dev = dev;
mtx_init(&sc->ciss_mtx, "cissmtx", NULL, MTX_DEF);
callout_init_mtx(&sc->ciss_periodic, &sc->ciss_mtx, 0);
/*
* Do PCI-specific init.
*/
if ((error = ciss_init_pci(sc)) != 0)
goto out;
/*
* Initialise driver queues.
*/
ciss_initq_free(sc);
ciss_initq_notify(sc);
/*
* Initialize device sysctls.
*/
ciss_init_sysctl(sc);
/*
* Initialise command/request pool.
*/
if ((error = ciss_init_requests(sc)) != 0)
goto out;
/*
* Get adapter information.
*/
if ((error = ciss_identify_adapter(sc)) != 0)
goto out;
/*
* Find all the physical devices.
*/
if ((error = ciss_init_physical(sc)) != 0)
goto out;
/*
* Build our private table of logical devices.
*/
if ((error = ciss_init_logical(sc)) != 0)
goto out;
/*
* Enable interrupts so that the CAM scan can complete.
*/
CISS_TL_SIMPLE_ENABLE_INTERRUPTS(sc);
/*
* Initialise the CAM interface.
*/
if ((error = ciss_cam_init(sc)) != 0)
goto out;
/*
* Start the heartbeat routine and event chain.
*/
ciss_periodic(sc);
/*
* Create the control device.
*/
sc->ciss_dev_t = make_dev(&ciss_cdevsw, device_get_unit(sc->ciss_dev),
UID_ROOT, GID_OPERATOR, S_IRUSR | S_IWUSR,
"ciss%d", device_get_unit(sc->ciss_dev));
sc->ciss_dev_t->si_drv1 = sc;
/*
* The adapter is running; synchronous commands can now sleep
* waiting for an interrupt to signal completion.
*/
sc->ciss_flags |= CISS_FLAG_RUNNING;
ciss_spawn_notify_thread(sc);
error = 0;
out:
if (error != 0) {
/* ciss_free() expects the mutex to be held */
mtx_lock(&sc->ciss_mtx);
ciss_free(sc);
}
return(error);
}
/************************************************************************
* Detach the driver from this adapter.
*/
static int
ciss_detach(device_t dev)
{
struct ciss_softc *sc = device_get_softc(dev);
debug_called(1);
mtx_lock(&sc->ciss_mtx);
if (sc->ciss_flags & CISS_FLAG_CONTROL_OPEN) {
mtx_unlock(&sc->ciss_mtx);
return (EBUSY);
}
/* flush adapter cache */
ciss_flush_adapter(sc);
/* release all resources. The mutex is released and freed here too. */
ciss_free(sc);
return(0);
}
/************************************************************************
* Prepare adapter for system shutdown.
*/
static int
ciss_shutdown(device_t dev)
{
struct ciss_softc *sc = device_get_softc(dev);
debug_called(1);
mtx_lock(&sc->ciss_mtx);
/* flush adapter cache */
ciss_flush_adapter(sc);
if (sc->ciss_soft_reset)
ciss_soft_reset(sc);
mtx_unlock(&sc->ciss_mtx);
return(0);
}
static void
ciss_init_sysctl(struct ciss_softc *sc)
{
SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->ciss_dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ciss_dev)),
OID_AUTO, "soft_reset", CTLFLAG_RW, &sc->ciss_soft_reset, 0, "");
}
/************************************************************************
* Perform PCI-specific attachment actions.
*/
static int
ciss_init_pci(struct ciss_softc *sc)
{
uintptr_t cbase, csize, cofs;
uint32_t method, supported_methods;
int error, sqmask, i;
void *intr;
debug_called(1);
/*
* Work out adapter type.
*/
i = ciss_lookup(sc->ciss_dev);
if (i < 0) {
ciss_printf(sc, "unknown adapter type\n");
return (ENXIO);
}
if (ciss_vendor_data[i].flags & CISS_BOARD_SA5) {
sqmask = CISS_TL_SIMPLE_INTR_OPQ_SA5;
} else if (ciss_vendor_data[i].flags & CISS_BOARD_SA5B) {
sqmask = CISS_TL_SIMPLE_INTR_OPQ_SA5B;
} else {
/*
* XXX Big hammer, masks/unmasks all possible interrupts. This should
* work on all hardware variants. Need to add code to handle the
* "controller crashed" interrupt bit that this unmasks.
*/
sqmask = ~0;
}
/*
* Allocate register window first (we need this to find the config
* struct).
*/
error = ENXIO;
sc->ciss_regs_rid = CISS_TL_SIMPLE_BAR_REGS;
if ((sc->ciss_regs_resource =
bus_alloc_resource_any(sc->ciss_dev, SYS_RES_MEMORY,
&sc->ciss_regs_rid, RF_ACTIVE)) == NULL) {
ciss_printf(sc, "can't allocate register window\n");
return(ENXIO);
}
sc->ciss_regs_bhandle = rman_get_bushandle(sc->ciss_regs_resource);
sc->ciss_regs_btag = rman_get_bustag(sc->ciss_regs_resource);
/*
* Find the BAR holding the config structure. If it's not the one
* we already mapped for registers, map it too.
*/
sc->ciss_cfg_rid = CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_CFG_BAR) & 0xffff;
if (sc->ciss_cfg_rid != sc->ciss_regs_rid) {
if ((sc->ciss_cfg_resource =
bus_alloc_resource_any(sc->ciss_dev, SYS_RES_MEMORY,
&sc->ciss_cfg_rid, RF_ACTIVE)) == NULL) {
ciss_printf(sc, "can't allocate config window\n");
return(ENXIO);
}
cbase = (uintptr_t)rman_get_virtual(sc->ciss_cfg_resource);
csize = rman_get_end(sc->ciss_cfg_resource) -
rman_get_start(sc->ciss_cfg_resource) + 1;
} else {
cbase = (uintptr_t)rman_get_virtual(sc->ciss_regs_resource);
csize = rman_get_end(sc->ciss_regs_resource) -
rman_get_start(sc->ciss_regs_resource) + 1;
}
cofs = CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_CFG_OFF);
/*
* Use the base/size/offset values we just calculated to
* sanity-check the config structure. If it's OK, point to it.
*/
if ((cofs + sizeof(struct ciss_config_table)) > csize) {
ciss_printf(sc, "config table outside window\n");
return(ENXIO);
}
sc->ciss_cfg = (struct ciss_config_table *)(cbase + cofs);
debug(1, "config struct at %p", sc->ciss_cfg);
/*
* Calculate the number of request structures/commands we are
* going to provide for this adapter.
*/
sc->ciss_max_requests = min(CISS_MAX_REQUESTS, sc->ciss_cfg->max_outstanding_commands);
/*
* Validate the config structure. If we supported other transport
* methods, we could select amongst them at this point in time.
*/
if (strncmp(sc->ciss_cfg->signature, "CISS", 4)) {
ciss_printf(sc, "config signature mismatch (got '%c%c%c%c')\n",
sc->ciss_cfg->signature[0], sc->ciss_cfg->signature[1],
sc->ciss_cfg->signature[2], sc->ciss_cfg->signature[3]);
return(ENXIO);
}
/*
* Select the mode of operation, prefer Performant.
*/
if (!(sc->ciss_cfg->supported_methods &
(CISS_TRANSPORT_METHOD_SIMPLE | CISS_TRANSPORT_METHOD_PERF))) {
ciss_printf(sc, "No supported transport layers: 0x%x\n",
sc->ciss_cfg->supported_methods);
}
switch (ciss_force_transport) {
case 1:
supported_methods = CISS_TRANSPORT_METHOD_SIMPLE;
break;
case 2:
supported_methods = CISS_TRANSPORT_METHOD_PERF;
break;
default:
/*
* Override the capabilities of the BOARD and specify SIMPLE
* MODE
*/
if (ciss_vendor_data[i].flags & CISS_BOARD_SIMPLE)
supported_methods = CISS_TRANSPORT_METHOD_SIMPLE;
else
supported_methods = sc->ciss_cfg->supported_methods;
break;
}
setup:
if ((supported_methods & CISS_TRANSPORT_METHOD_PERF) != 0) {
method = CISS_TRANSPORT_METHOD_PERF;
sc->ciss_perf = (struct ciss_perf_config *)(cbase + cofs +
sc->ciss_cfg->transport_offset);
if (ciss_init_perf(sc)) {
supported_methods &= ~method;
goto setup;
}
} else if (supported_methods & CISS_TRANSPORT_METHOD_SIMPLE) {
method = CISS_TRANSPORT_METHOD_SIMPLE;
} else {
ciss_printf(sc, "No supported transport methods: 0x%x\n",
sc->ciss_cfg->supported_methods);
return(ENXIO);
}
/*
* Tell it we're using the low 4GB of RAM. Set the default interrupt
* coalescing options.
*/
sc->ciss_cfg->requested_method = method;
sc->ciss_cfg->command_physlimit = 0;
sc->ciss_cfg->interrupt_coalesce_delay = CISS_INTERRUPT_COALESCE_DELAY;
sc->ciss_cfg->interrupt_coalesce_count = CISS_INTERRUPT_COALESCE_COUNT;
#ifdef __i386__
sc->ciss_cfg->host_driver |= CISS_DRIVER_SCSI_PREFETCH;
#endif
if (ciss_update_config(sc)) {
ciss_printf(sc, "adapter refuses to accept config update (IDBR 0x%x)\n",
CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IDBR));
return(ENXIO);
}
if ((sc->ciss_cfg->active_method & method) == 0) {
supported_methods &= ~method;
if (supported_methods == 0) {
ciss_printf(sc, "adapter refuses to go into available transports "
"mode (0x%x, 0x%x)\n", supported_methods,
sc->ciss_cfg->active_method);
return(ENXIO);
} else
goto setup;
}
/*
* Wait for the adapter to come ready.
*/
if ((error = ciss_wait_adapter(sc)) != 0)
return(error);
/* Prepare to possibly use MSIX and/or PERFORMANT interrupts. Normal
* interrupts have a rid of 0, this will be overridden if MSIX is used.
*/
sc->ciss_irq_rid[0] = 0;
if (method == CISS_TRANSPORT_METHOD_PERF) {
ciss_printf(sc, "PERFORMANT Transport\n");
if ((ciss_force_interrupt != 1) && (ciss_setup_msix(sc) == 0)) {
intr = ciss_perf_msi_intr;
} else {
intr = ciss_perf_intr;
}
/* XXX The docs say that the 0x01 bit is only for SAS controllers.
* Unfortunately, there is no good way to know if this is a SAS
* controller. Hopefully enabling this bit universally will work OK.
* It seems to work fine for SA6i controllers.
*/
sc->ciss_interrupt_mask = CISS_TL_PERF_INTR_OPQ | CISS_TL_PERF_INTR_MSI;
} else {
ciss_printf(sc, "SIMPLE Transport\n");
/* MSIX doesn't seem to work in SIMPLE mode, only enable if it forced */
if (ciss_force_interrupt == 2)
/* If this fails, we automatically revert to INTx */
ciss_setup_msix(sc);
sc->ciss_perf = NULL;
intr = ciss_intr;
sc->ciss_interrupt_mask = sqmask;
}
/*
* Turn off interrupts before we go routing anything.
*/
CISS_TL_SIMPLE_DISABLE_INTERRUPTS(sc);
/*
* Allocate and set up our interrupt.
*/
if ((sc->ciss_irq_resource =
bus_alloc_resource_any(sc->ciss_dev, SYS_RES_IRQ, &sc->ciss_irq_rid[0],
RF_ACTIVE | RF_SHAREABLE)) == NULL) {
ciss_printf(sc, "can't allocate interrupt\n");
return(ENXIO);
}
if (bus_setup_intr(sc->ciss_dev, sc->ciss_irq_resource,
INTR_TYPE_CAM|INTR_MPSAFE, NULL, intr, sc,
&sc->ciss_intr)) {
ciss_printf(sc, "can't set up interrupt\n");
return(ENXIO);
}
/*
* Allocate the parent bus DMA tag appropriate for our PCI
* interface.
*
* Note that "simple" adapters can only address within a 32-bit
* span.
*/
if (bus_dma_tag_create(bus_get_dma_tag(sc->ciss_dev),/* PCI parent */
1, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
BUS_SPACE_UNRESTRICTED, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->ciss_parent_dmat)) {
ciss_printf(sc, "can't allocate parent DMA tag\n");
return(ENOMEM);
}
/*
* Create DMA tag for mapping buffers into adapter-addressable
* space.
*/
if (bus_dma_tag_create(sc->ciss_parent_dmat, /* parent */
1, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
(CISS_MAX_SG_ELEMENTS - 1) * PAGE_SIZE, /* maxsize */
CISS_MAX_SG_ELEMENTS, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
BUS_DMA_ALLOCNOW, /* flags */
busdma_lock_mutex, &sc->ciss_mtx, /* lockfunc, lockarg */
&sc->ciss_buffer_dmat)) {
ciss_printf(sc, "can't allocate buffer DMA tag\n");
return(ENOMEM);
}
return(0);
}
/************************************************************************
* Setup MSI/MSIX operation (Performant only)
* Four interrupts are available, but we only use 1 right now. If MSI-X
* isn't avaialble, try using MSI instead.
*/
static int
ciss_setup_msix(struct ciss_softc *sc)
{
int val, i;
/* Weed out devices that don't actually support MSI */
i = ciss_lookup(sc->ciss_dev);
if (ciss_vendor_data[i].flags & CISS_BOARD_NOMSI)
return (EINVAL);
/*
* Only need to use the minimum number of MSI vectors, as the driver
* doesn't support directed MSIX interrupts.
*/
val = pci_msix_count(sc->ciss_dev);
if (val < CISS_MSI_COUNT) {
val = pci_msi_count(sc->ciss_dev);
device_printf(sc->ciss_dev, "got %d MSI messages]\n", val);
if (val < CISS_MSI_COUNT)
return (EINVAL);
}
val = MIN(val, CISS_MSI_COUNT);
if (pci_alloc_msix(sc->ciss_dev, &val) != 0) {
if (pci_alloc_msi(sc->ciss_dev, &val) != 0)
return (EINVAL);
}
sc->ciss_msi = val;
if (bootverbose)
ciss_printf(sc, "Using %d MSIX interrupt%s\n", val,
(val != 1) ? "s" : "");
for (i = 0; i < val; i++)
sc->ciss_irq_rid[i] = i + 1;
return (0);
}
/************************************************************************
* Setup the Performant structures.
*/
static int
ciss_init_perf(struct ciss_softc *sc)
{
struct ciss_perf_config *pc = sc->ciss_perf;
int reply_size;
/*
* Create the DMA tag for the reply queue.
*/
reply_size = sizeof(uint64_t) * sc->ciss_max_requests;
if (bus_dma_tag_create(sc->ciss_parent_dmat, /* parent */
1, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
reply_size, 1, /* maxsize, nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->ciss_reply_dmat)) {
ciss_printf(sc, "can't allocate reply DMA tag\n");
return(ENOMEM);
}
/*
* Allocate memory and make it available for DMA.
*/
if (bus_dmamem_alloc(sc->ciss_reply_dmat, (void **)&sc->ciss_reply,
BUS_DMA_NOWAIT, &sc->ciss_reply_map)) {
ciss_printf(sc, "can't allocate reply memory\n");
return(ENOMEM);
}
bus_dmamap_load(sc->ciss_reply_dmat, sc->ciss_reply_map, sc->ciss_reply,
reply_size, ciss_command_map_helper, &sc->ciss_reply_phys, 0);
bzero(sc->ciss_reply, reply_size);
sc->ciss_cycle = 0x1;
sc->ciss_rqidx = 0;
/*
* Preload the fetch table with common command sizes. This allows the
* hardware to not waste bus cycles for typical i/o commands, but also not
* tax the driver to be too exact in choosing sizes. The table is optimized
* for page-aligned i/o's, but since most i/o comes from the various pagers,
* it's a reasonable assumption to make.
*/
pc->fetch_count[CISS_SG_FETCH_NONE] = (sizeof(struct ciss_command) + 15) / 16;
pc->fetch_count[CISS_SG_FETCH_1] =
(sizeof(struct ciss_command) + sizeof(struct ciss_sg_entry) * 1 + 15) / 16;
pc->fetch_count[CISS_SG_FETCH_2] =
(sizeof(struct ciss_command) + sizeof(struct ciss_sg_entry) * 2 + 15) / 16;
pc->fetch_count[CISS_SG_FETCH_4] =
(sizeof(struct ciss_command) + sizeof(struct ciss_sg_entry) * 4 + 15) / 16;
pc->fetch_count[CISS_SG_FETCH_8] =
(sizeof(struct ciss_command) + sizeof(struct ciss_sg_entry) * 8 + 15) / 16;
pc->fetch_count[CISS_SG_FETCH_16] =
(sizeof(struct ciss_command) + sizeof(struct ciss_sg_entry) * 16 + 15) / 16;
pc->fetch_count[CISS_SG_FETCH_32] =
(sizeof(struct ciss_command) + sizeof(struct ciss_sg_entry) * 32 + 15) / 16;
pc->fetch_count[CISS_SG_FETCH_MAX] = (CISS_COMMAND_ALLOC_SIZE + 15) / 16;
pc->rq_size = sc->ciss_max_requests; /* XXX less than the card supports? */
pc->rq_count = 1; /* XXX Hardcode for a single queue */
pc->rq_bank_hi = 0;
pc->rq_bank_lo = 0;
pc->rq[0].rq_addr_hi = 0x0;
pc->rq[0].rq_addr_lo = sc->ciss_reply_phys;
return(0);
}
/************************************************************************
* Wait for the adapter to come ready.
*/
static int
ciss_wait_adapter(struct ciss_softc *sc)
{
int i;
debug_called(1);
/*
* Wait for the adapter to come ready.