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if_dc.c
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if_dc.c
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/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
* series chips and several workalikes including the following:
*
* Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
* Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
* Lite-On 82c168/82c169 PNIC (www.litecom.com)
* ASIX Electronics AX88140A (www.asix.com.tw)
* ASIX Electronics AX88141 (www.asix.com.tw)
* ADMtek AL981 (www.admtek.com.tw)
* ADMtek AN983 (www.admtek.com.tw)
* ADMtek CardBus AN985 (www.admtek.com.tw)
* Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985
* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
* Accton EN1217 (www.accton.com)
* Xircom X3201 (www.xircom.com)
* Abocom FE2500
* Conexant LANfinity (www.conexant.com)
* 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
*
* Datasheets for the 21143 are available at developer.intel.com.
* Datasheets for the clone parts can be found at their respective sites.
* (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
* The PNIC II is essentially a Macronix 98715A chip; the only difference
* worth noting is that its multicast hash table is only 128 bits wide
* instead of 512.
*
* Written by Bill Paul <wpaul@ee.columbia.edu>
* Electrical Engineering Department
* Columbia University, New York City
*/
/*
* The Intel 21143 is the successor to the DEC 21140. It is basically
* the same as the 21140 but with a few new features. The 21143 supports
* three kinds of media attachments:
*
* o MII port, for 10Mbps and 100Mbps support and NWAY
* autonegotiation provided by an external PHY.
* o SYM port, for symbol mode 100Mbps support.
* o 10baseT port.
* o AUI/BNC port.
*
* The 100Mbps SYM port and 10baseT port can be used together in
* combination with the internal NWAY support to create a 10/100
* autosensing configuration.
*
* Note that not all tulip workalikes are handled in this driver: we only
* deal with those which are relatively well behaved. The Winbond is
* handled separately due to its different register offsets and the
* special handling needed for its various bugs. The PNIC is handled
* here, but I'm not thrilled about it.
*
* All of the workalike chips use some form of MII transceiver support
* with the exception of the Macronix chips, which also have a SYM port.
* The ASIX AX88140A is also documented to have a SYM port, but all
* the cards I've seen use an MII transceiver, probably because the
* AX88140A doesn't support internal NWAY.
*/
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_device_polling.h"
#endif
#include <sys/param.h>
#include <sys/endian.h>
#include <sys/systm.h>
#include <sys/sockio.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/socket.h>
#include <net/if.h>
#include <net/if_var.h>
#include <net/if_arp.h>
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/if_types.h>
#include <net/if_vlan_var.h>
#include <net/bpf.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <dev/mii/mii.h>
#include <dev/mii/mii_bitbang.h>
#include <dev/mii/miivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#define DC_USEIOSPACE
#include <dev/dc/if_dcreg.h>
#ifdef __sparc64__
#include <dev/ofw/openfirm.h>
#include <machine/ofw_machdep.h>
#endif
MODULE_DEPEND(dc, pci, 1, 1, 1);
MODULE_DEPEND(dc, ether, 1, 1, 1);
MODULE_DEPEND(dc, miibus, 1, 1, 1);
/*
* "device miibus" is required in kernel config. See GENERIC if you get
* errors here.
*/
#include "miibus_if.h"
/*
* Various supported device vendors/types and their names.
*/
static const struct dc_type dc_devs[] = {
{ DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
"Intel 21143 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
"Davicom DM9009 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
"Davicom DM9100 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
"Davicom DM9102A 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
"Davicom DM9102 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
"ADMtek AL981 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0,
"ADMtek AN983 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
"ADMtek AN985 CardBus 10/100BaseTX or clone" },
{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
"ADMtek ADM9511 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
"ADMtek ADM9513 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
"ASIX AX88141 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
"ASIX AX88140A 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
"Macronix 98713A 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
"Macronix 98713 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
"Compex RL100-TX 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
"Compex RL100-TX 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
"Macronix 98725 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
"Macronix 98715AEC-C 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
"Macronix 98715/98715A 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
"Macronix 98727/98732 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
"LC82C115 PNIC II 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
"82c169 PNIC 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
"82c168 PNIC 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
"Accton EN1217 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
"Accton EN2242 MiniPCI 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
"Xircom X3201 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
"Neteasy DRP-32TXD Cardbus 10/100" },
{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
"Abocom FE2500 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
"Abocom FE2500MX 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
"Conexant LANfinity MiniPCI 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
"Hawking CB102 CardBus 10/100" },
{ DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
"PlaneX FNW-3602-T CardBus 10/100" },
{ DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
"3Com OfficeConnect 10/100B" },
{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
"Microsoft MN-120 CardBus 10/100" },
{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
"Microsoft MN-130 10/100" },
{ DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
"Linksys PCMPC200 CardBus 10/100" },
{ DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
"Linksys PCMPC200 CardBus 10/100" },
{ DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0,
"ULi M5261 FastEthernet" },
{ DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0,
"ULi M5263 FastEthernet" },
{ 0, 0, NULL }
};
static int dc_probe(device_t);
static int dc_attach(device_t);
static int dc_detach(device_t);
static int dc_suspend(device_t);
static int dc_resume(device_t);
static const struct dc_type *dc_devtype(device_t);
static void dc_discard_rxbuf(struct dc_softc *, int);
static int dc_newbuf(struct dc_softc *, int);
static int dc_encap(struct dc_softc *, struct mbuf **);
static void dc_pnic_rx_bug_war(struct dc_softc *, int);
static int dc_rx_resync(struct dc_softc *);
static int dc_rxeof(struct dc_softc *);
static void dc_txeof(struct dc_softc *);
static void dc_tick(void *);
static void dc_tx_underrun(struct dc_softc *);
static void dc_intr(void *);
static void dc_start(struct ifnet *);
static void dc_start_locked(struct ifnet *);
static int dc_ioctl(struct ifnet *, u_long, caddr_t);
static void dc_init(void *);
static void dc_init_locked(struct dc_softc *);
static void dc_stop(struct dc_softc *);
static void dc_watchdog(void *);
static int dc_shutdown(device_t);
static int dc_ifmedia_upd(struct ifnet *);
static int dc_ifmedia_upd_locked(struct dc_softc *);
static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
static int dc_dma_alloc(struct dc_softc *);
static void dc_dma_free(struct dc_softc *);
static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int);
static void dc_delay(struct dc_softc *);
static void dc_eeprom_idle(struct dc_softc *);
static void dc_eeprom_putbyte(struct dc_softc *, int);
static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *);
static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *);
static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *);
static void dc_eeprom_width(struct dc_softc *);
static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
static int dc_miibus_readreg(device_t, int, int);
static int dc_miibus_writereg(device_t, int, int, int);
static void dc_miibus_statchg(device_t);
static void dc_miibus_mediainit(device_t);
static void dc_setcfg(struct dc_softc *, int);
static void dc_netcfg_wait(struct dc_softc *);
static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
static uint32_t dc_mchash_be(const uint8_t *);
static void dc_setfilt_21143(struct dc_softc *);
static void dc_setfilt_asix(struct dc_softc *);
static void dc_setfilt_admtek(struct dc_softc *);
static void dc_setfilt_uli(struct dc_softc *);
static void dc_setfilt_xircom(struct dc_softc *);
static void dc_setfilt(struct dc_softc *);
static void dc_reset(struct dc_softc *);
static int dc_list_rx_init(struct dc_softc *);
static int dc_list_tx_init(struct dc_softc *);
static int dc_read_srom(struct dc_softc *, int);
static int dc_parse_21143_srom(struct dc_softc *);
static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
static void dc_apply_fixup(struct dc_softc *, int);
static int dc_check_multiport(struct dc_softc *);
/*
* MII bit-bang glue
*/
static uint32_t dc_mii_bitbang_read(device_t);
static void dc_mii_bitbang_write(device_t, uint32_t);
static const struct mii_bitbang_ops dc_mii_bitbang_ops = {
dc_mii_bitbang_read,
dc_mii_bitbang_write,
{
DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */
DC_SIO_MII_DATAIN, /* MII_BIT_MDI */
DC_SIO_MII_CLK, /* MII_BIT_MDC */
0, /* MII_BIT_DIR_HOST_PHY */
DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */
}
};
#ifdef DC_USEIOSPACE
#define DC_RES SYS_RES_IOPORT
#define DC_RID DC_PCI_CFBIO
#else
#define DC_RES SYS_RES_MEMORY
#define DC_RID DC_PCI_CFBMA
#endif
static device_method_t dc_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, dc_probe),
DEVMETHOD(device_attach, dc_attach),
DEVMETHOD(device_detach, dc_detach),
DEVMETHOD(device_suspend, dc_suspend),
DEVMETHOD(device_resume, dc_resume),
DEVMETHOD(device_shutdown, dc_shutdown),
/* MII interface */
DEVMETHOD(miibus_readreg, dc_miibus_readreg),
DEVMETHOD(miibus_writereg, dc_miibus_writereg),
DEVMETHOD(miibus_statchg, dc_miibus_statchg),
DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
DEVMETHOD_END
};
static driver_t dc_driver = {
"dc",
dc_methods,
sizeof(struct dc_softc)
};
static devclass_t dc_devclass;
DRIVER_MODULE_ORDERED(dc, pci, dc_driver, dc_devclass, NULL, NULL,
SI_ORDER_ANY);
MODULE_PNP_INFO("W32:vendor/device;U8:revision;D:#", pci, dc, dc_devs,
nitems(dc_devs) - 1);
DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL);
#define DC_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
#define DC_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
static void
dc_delay(struct dc_softc *sc)
{
int idx;
for (idx = (300 / 33) + 1; idx > 0; idx--)
CSR_READ_4(sc, DC_BUSCTL);
}
static void
dc_eeprom_width(struct dc_softc *sc)
{
int i;
/* Force EEPROM to idle state. */
dc_eeprom_idle(sc);
/* Enter EEPROM access mode. */
CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
dc_delay(sc);
for (i = 3; i--;) {
if (6 & (1 << i))
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
else
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
}
for (i = 1; i <= 12; i++) {
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
break;
}
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
}
/* Turn off EEPROM access mode. */
dc_eeprom_idle(sc);
if (i < 4 || i > 12)
sc->dc_romwidth = 6;
else
sc->dc_romwidth = i;
/* Enter EEPROM access mode. */
CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
dc_delay(sc);
/* Turn off EEPROM access mode. */
dc_eeprom_idle(sc);
}
static void
dc_eeprom_idle(struct dc_softc *sc)
{
int i;
CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
dc_delay(sc);
for (i = 0; i < 25; i++) {
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
}
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
dc_delay(sc);
CSR_WRITE_4(sc, DC_SIO, 0x00000000);
}
/*
* Send a read command and address to the EEPROM, check for ACK.
*/
static void
dc_eeprom_putbyte(struct dc_softc *sc, int addr)
{
int d, i;
d = DC_EECMD_READ >> 6;
for (i = 3; i--; ) {
if (d & (1 << i))
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
else
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
}
/*
* Feed in each bit and strobe the clock.
*/
for (i = sc->dc_romwidth; i--;) {
if (addr & (1 << i)) {
SIO_SET(DC_SIO_EE_DATAIN);
} else {
SIO_CLR(DC_SIO_EE_DATAIN);
}
dc_delay(sc);
SIO_SET(DC_SIO_EE_CLK);
dc_delay(sc);
SIO_CLR(DC_SIO_EE_CLK);
dc_delay(sc);
}
}
/*
* Read a word of data stored in the EEPROM at address 'addr.'
* The PNIC 82c168/82c169 has its own non-standard way to read
* the EEPROM.
*/
static void
dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest)
{
int i;
uint32_t r;
CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
for (i = 0; i < DC_TIMEOUT; i++) {
DELAY(1);
r = CSR_READ_4(sc, DC_SIO);
if (!(r & DC_PN_SIOCTL_BUSY)) {
*dest = (uint16_t)(r & 0xFFFF);
return;
}
}
}
/*
* Read a word of data stored in the EEPROM at address 'addr.'
* The Xircom X3201 has its own non-standard way to read
* the EEPROM, too.
*/
static void
dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest)
{
SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
addr *= 2;
CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
*dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
addr += 1;
CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
*dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
}
/*
* Read a word of data stored in the EEPROM at address 'addr.'
*/
static void
dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest)
{
int i;
uint16_t word = 0;
/* Force EEPROM to idle state. */
dc_eeprom_idle(sc);
/* Enter EEPROM access mode. */
CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
dc_delay(sc);
/*
* Send address of word we want to read.
*/
dc_eeprom_putbyte(sc, addr);
/*
* Start reading bits from EEPROM.
*/
for (i = 0x8000; i; i >>= 1) {
SIO_SET(DC_SIO_EE_CLK);
dc_delay(sc);
if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
word |= i;
dc_delay(sc);
SIO_CLR(DC_SIO_EE_CLK);
dc_delay(sc);
}
/* Turn off EEPROM access mode. */
dc_eeprom_idle(sc);
*dest = word;
}
/*
* Read a sequence of words from the EEPROM.
*/
static void
dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
{
int i;
uint16_t word = 0, *ptr;
for (i = 0; i < cnt; i++) {
if (DC_IS_PNIC(sc))
dc_eeprom_getword_pnic(sc, off + i, &word);
else if (DC_IS_XIRCOM(sc))
dc_eeprom_getword_xircom(sc, off + i, &word);
else
dc_eeprom_getword(sc, off + i, &word);
ptr = (uint16_t *)(dest + (i * 2));
if (be)
*ptr = be16toh(word);
else
*ptr = le16toh(word);
}
}
/*
* Write the MII serial port for the MII bit-bang module.
*/
static void
dc_mii_bitbang_write(device_t dev, uint32_t val)
{
struct dc_softc *sc;
sc = device_get_softc(dev);
CSR_WRITE_4(sc, DC_SIO, val);
CSR_BARRIER_4(sc, DC_SIO,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
}
/*
* Read the MII serial port for the MII bit-bang module.
*/
static uint32_t
dc_mii_bitbang_read(device_t dev)
{
struct dc_softc *sc;
uint32_t val;
sc = device_get_softc(dev);
val = CSR_READ_4(sc, DC_SIO);
CSR_BARRIER_4(sc, DC_SIO,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
return (val);
}
static int
dc_miibus_readreg(device_t dev, int phy, int reg)
{
struct dc_softc *sc;
int i, rval, phy_reg = 0;
sc = device_get_softc(dev);
if (sc->dc_pmode != DC_PMODE_MII) {
if (phy == (MII_NPHY - 1)) {
switch (reg) {
case MII_BMSR:
/*
* Fake something to make the probe
* code think there's a PHY here.
*/
return (BMSR_MEDIAMASK);
case MII_PHYIDR1:
if (DC_IS_PNIC(sc))
return (DC_VENDORID_LO);
return (DC_VENDORID_DEC);
case MII_PHYIDR2:
if (DC_IS_PNIC(sc))
return (DC_DEVICEID_82C168);
return (DC_DEVICEID_21143);
default:
return (0);
}
} else
return (0);
}
if (DC_IS_PNIC(sc)) {
CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
(phy << 23) | (reg << 18));
for (i = 0; i < DC_TIMEOUT; i++) {
DELAY(1);
rval = CSR_READ_4(sc, DC_PN_MII);
if (!(rval & DC_PN_MII_BUSY)) {
rval &= 0xFFFF;
return (rval == 0xFFFF ? 0 : rval);
}
}
return (0);
}
if (sc->dc_type == DC_TYPE_ULI_M5263) {
CSR_WRITE_4(sc, DC_ROM,
((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
DC_ULI_PHY_OP_READ);
for (i = 0; i < DC_TIMEOUT; i++) {
DELAY(1);
rval = CSR_READ_4(sc, DC_ROM);
if ((rval & DC_ULI_PHY_OP_DONE) != 0) {
return (rval & DC_ULI_PHY_DATA_MASK);
}
}
if (i == DC_TIMEOUT)
device_printf(dev, "phy read timed out\n");
return (0);
}
if (DC_IS_COMET(sc)) {
switch (reg) {
case MII_BMCR:
phy_reg = DC_AL_BMCR;
break;
case MII_BMSR:
phy_reg = DC_AL_BMSR;
break;
case MII_PHYIDR1:
phy_reg = DC_AL_VENID;
break;
case MII_PHYIDR2:
phy_reg = DC_AL_DEVID;
break;
case MII_ANAR:
phy_reg = DC_AL_ANAR;
break;
case MII_ANLPAR:
phy_reg = DC_AL_LPAR;
break;
case MII_ANER:
phy_reg = DC_AL_ANER;
break;
default:
device_printf(dev, "phy_read: bad phy register %x\n",
reg);
return (0);
}
rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
if (rval == 0xFFFF)
return (0);
return (rval);
}
if (sc->dc_type == DC_TYPE_98713) {
phy_reg = CSR_READ_4(sc, DC_NETCFG);
CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
}
rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg);
if (sc->dc_type == DC_TYPE_98713)
CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
return (rval);
}
static int
dc_miibus_writereg(device_t dev, int phy, int reg, int data)
{
struct dc_softc *sc;
int i, phy_reg = 0;
sc = device_get_softc(dev);
if (DC_IS_PNIC(sc)) {
CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
(phy << 23) | (reg << 10) | data);
for (i = 0; i < DC_TIMEOUT; i++) {
if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
break;
}
return (0);
}
if (sc->dc_type == DC_TYPE_ULI_M5263) {
CSR_WRITE_4(sc, DC_ROM,
((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) |
DC_ULI_PHY_OP_WRITE);
DELAY(1);
return (0);
}
if (DC_IS_COMET(sc)) {
switch (reg) {
case MII_BMCR:
phy_reg = DC_AL_BMCR;
break;
case MII_BMSR:
phy_reg = DC_AL_BMSR;
break;
case MII_PHYIDR1:
phy_reg = DC_AL_VENID;
break;
case MII_PHYIDR2:
phy_reg = DC_AL_DEVID;
break;
case MII_ANAR:
phy_reg = DC_AL_ANAR;
break;
case MII_ANLPAR:
phy_reg = DC_AL_LPAR;
break;
case MII_ANER:
phy_reg = DC_AL_ANER;
break;
default:
device_printf(dev, "phy_write: bad phy register %x\n",
reg);
return (0);
break;
}
CSR_WRITE_4(sc, phy_reg, data);
return (0);
}
if (sc->dc_type == DC_TYPE_98713) {
phy_reg = CSR_READ_4(sc, DC_NETCFG);
CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
}
mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data);
if (sc->dc_type == DC_TYPE_98713)
CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
return (0);
}
static void
dc_miibus_statchg(device_t dev)
{
struct dc_softc *sc;
struct ifnet *ifp;
struct mii_data *mii;
struct ifmedia *ifm;
sc = device_get_softc(dev);
mii = device_get_softc(sc->dc_miibus);
ifp = sc->dc_ifp;
if (mii == NULL || ifp == NULL ||
(ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
return;
ifm = &mii->mii_media;
if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
dc_setcfg(sc, ifm->ifm_media);
return;
} else if (!DC_IS_ADMTEK(sc))
dc_setcfg(sc, mii->mii_media_active);
sc->dc_link = 0;
if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
(IFM_ACTIVE | IFM_AVALID)) {
switch (IFM_SUBTYPE(mii->mii_media_active)) {
case IFM_10_T:
case IFM_100_TX:
sc->dc_link = 1;
break;
}
}
}
/*
* Special support for DM9102A cards with HomePNA PHYs. Note:
* with the Davicom DM9102A/DM9801 eval board that I have, it seems
* to be impossible to talk to the management interface of the DM9801
* PHY (its MDIO pin is not connected to anything). Consequently,
* the driver has to just 'know' about the additional mode and deal
* with it itself. *sigh*
*/
static void
dc_miibus_mediainit(device_t dev)
{
struct dc_softc *sc;
struct mii_data *mii;
struct ifmedia *ifm;
int rev;
rev = pci_get_revid(dev);
sc = device_get_softc(dev);
mii = device_get_softc(sc->dc_miibus);
ifm = &mii->mii_media;
if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
}
#define DC_BITS_512 9
#define DC_BITS_128 7
#define DC_BITS_64 6
static uint32_t
dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
{
uint32_t crc;
/* Compute CRC for the address value. */
crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
/*
* The hash table on the PNIC II and the MX98715AEC-C/D/E
* chips is only 128 bits wide.
*/
if (sc->dc_flags & DC_128BIT_HASH)
return (crc & ((1 << DC_BITS_128) - 1));
/* The hash table on the MX98715BEC is only 64 bits wide. */
if (sc->dc_flags & DC_64BIT_HASH)
return (crc & ((1 << DC_BITS_64) - 1));
/* Xircom's hash filtering table is different (read: weird) */
/* Xircom uses the LEAST significant bits */
if (DC_IS_XIRCOM(sc)) {
if ((crc & 0x180) == 0x180)
return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
else
return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
(12 << 4));
}
return (crc & ((1 << DC_BITS_512) - 1));
}
/*
* Calculate CRC of a multicast group address, return the lower 6 bits.
*/
static uint32_t
dc_mchash_be(const uint8_t *addr)
{
uint32_t crc;
/* Compute CRC for the address value. */
crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
/* Return the filter bit position. */
return ((crc >> 26) & 0x0000003F);
}
/*
* 21143-style RX filter setup routine. Filter programming is done by
* downloading a special setup frame into the TX engine. 21143, Macronix,
* PNIC, PNIC II and Davicom chips are programmed this way.
*
* We always program the chip using 'hash perfect' mode, i.e. one perfect
* address (our node address) and a 512-bit hash filter for multicast
* frames. We also sneak the broadcast address into the hash filter since
* we need that too.
*/
static void
dc_setfilt_21143(struct dc_softc *sc)
{
uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
struct dc_desc *sframe;
uint32_t h, *sp;
struct ifmultiaddr *ifma;
struct ifnet *ifp;
int i;
ifp = sc->dc_ifp;
i = sc->dc_cdata.dc_tx_prod;
DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
sc->dc_cdata.dc_tx_cnt++;
sframe = &sc->dc_ldata.dc_tx_list[i];
sp = sc->dc_cdata.dc_sbuf;
bzero(sp, DC_SFRAME_LEN);
sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
/* If we want promiscuous mode, set the allframes bit. */
if (ifp->if_flags & IFF_PROMISC)
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
else
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
if (ifp->if_flags & IFF_ALLMULTI)
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
else
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);